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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37273MF-XXXSP M37273EFSP
DESCRIPTION
The M37273MF-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37273MF-XXXSP has a OSD function and a data slicer function, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37273EFSP are similar to those of the M37273MF-XXXSP except that these chips have a builtin PROM which can be written electrically.
* OSD function
Display characters ................................. 32 characters ! 2 lines (16 lines maximum) Kinds of characters ..................................................... 254 kinds Character display area ........................ CC mode : 16 ! 26 dots OSD mode : 16 ! 20 dots Kinds of character sizes ................................. CC mode : 1 type OSD mode : 8 types Kinds of character colors (It can be specified by the character) maximum 7 kinds Kings of character background colors ... CC mode : 1 type (black) OSD mode : 7 types (It can be specified by the character) Display position Horizontal ................................................................ 128 levels Vertical .................................................................... 512 levels Attribute ...................... CC mode : smooth italic, underline, flash OSD mode : border Kinds of raster colors (maximum 7 kinds) Smooth roll-up function Window function Automatic solid space
FEATURES
* Number of basic instructions ..................................................... 71 * Memory size
ROM ....................................................... 60 K bytes RAM ........................................................ 1472 bytes (including ROM correction memory: 64 bytes) ROM for OSD ......................................... 10 K bytes RAM for OSD ............................................ 128 bytes Minimum instruction execution time ......................................... 0.5 s (at 8 MHz oscillation frequency) Power source voltage................................................... 5 V 10 % Subroutine nesting ............................................. 128 levels (Max.) Interrupts ....................................................... 17 types, 16 vectors 8-bit timers .................................................................................. 6 Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26 Input ports (Ports P50, P51) ........................................................ 2 Output ports (Ports P52-P57, P6) ............................................. 14 12 V withstand ports .................................................................... 6 LED drive ports ........................................................................... 4 Serial I/O ............................................................ 8-bit ! 1 channel Multi-master I2C-BUS interface ................................ 1 (2 systems) A-D comparator (6-bit resolution) ................................. 6 channels PWM output circuit (8-bit)................................................ 8-bit ! 6 ROM correction function ........................................... 32 bytes ! 2 Power dissipation In high-speed mode .......................................................... 165mW (at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data slicer on) In low-speed mode ........................................................... 0.33mW (at VCC = 5.5V, 32 kHz oscillation frequency) Data slicer
* * * * * * * * * * * * * * * *
APPLICATION
TV with a closed caption decoder
*
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PIN CONFIGURATION (TOP VIEW)
P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P56 P02/PWM2 P57 P03/PWM3 P60 P04/PWM4 P05/PWM5 P06/INT2/AD4 P61 P07/INT1 P62 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS
1 2 3 4 5 6
52 51 50 49 48 47
P52/R P53/G P54/B P55/OUT1 P63 P20/SCLK P64 P21/SOUT P65 P22/SIN P66 P10/OUT2 P67 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC
M37273MF-XXXSP, M37273EFSP
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Outline 52P4B
2
FUNCTIONAL BLOCK DIAGRAM of M37273MF-XXXSP
Clock input Clock output Reset input RESET AVCC VCC VSS CNVSS
26 23 22 21 20 29 28
XIN XOUT
30 19 27
Pins for data slicer CVIN VHOLD HLF
I/O ports P26, P27 Clock input for OSD/ Clock output for OSD/ sub-clock input sub-clock output OSC1/XCIN OSC2/XCOUT
24
25
Clock generating circuit
Data slicer
Data bus Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8)
TIM2 TIM3
ROM correction circuit PCH (8) PCL (8)
RAM 1472 bytes ROM 60K bytes
Program counter Program counter
Address bus
Timer 4 T4 (8)
Index register Index register
Control signal
8-bit arithmetic and logical unit X (8) Y (8) Stack pointer S (8) Timer 5 T5 (8) Timer 6 T6 (8)
Accumulator A (8)
Processor status register PS (8)
Instruction decoder Instruction register (8) CRT circuit
INT1 INT2 INT3
A-D comparator
SDA2 SDA1 SCL2 SCL1
Multi-master I2C-BUS interface
SI/O
PWM
SIN SCLK SOUT
PWM5
PWM4
PWM3
PWM2 PWM1 PWM0
P0 (8)
P1 (8)
P2 (6) P3 (2)
P6 (8)
OUT2 P10
AD1-AD6
P5 (8)
OUT1 B G R VSYNC HSYNC
14 12 11 10 8 6 4 3 18 17 16 43 45 47
33 34 35 36 37 38 39 41
31 32
40 42 44 46 48 15 13 9
7 5 49 50 51 52 2 1
I/O port P0 I/O port P2
I/O port P1
I/O ports P30, P31
Output ports P6
Output ports P52-P57 Output for display Input ports P50, P51 Synchronous signal input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
3
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONS
Parameter Number of basic instructions Instruction execution time Clock frequency Memory size Functions 71 0.5 s (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 60 K bytes 1472 bytes (including ROM correction memory : 64 bytes) 10 K bytes 128 bytes 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, AD input pin) 8-bit ! 1 (P10 and P15-P17: CMOS input/output structure, P11-P14: CMOS input/output or N-channel open-drain output structure, can be used as OSD output pin, AD input pins, INT input pin, multi-master I2C-BUS interface) 8-bit ! 1 (P20 and P21: CMOS input/output or N-channel open-drain output structure, P22-P27: CMOS input/output structure, can be used as serial input/output pins, external clock input pins) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as AD input pins) 2-bit ! 1 (can be used as OSD input pins) 14-bit ! 1 (CMOS output structure, can be used as OSD output pins) 8-bit ! 1 1 (2 systems) 6 channels (6-bit resolution) 8-bit ! 6 8-bit timer ! 6 32 bytes ! 2 128 levels (maximum) External interrupt ! 3, Internal timer interrupt ! 6, Serial I/O interrupt ! 1, OSD interrupt ! 1, Multi-master I2C-BUS interface interrupt ! 1, Data slicer interrupt ! 1, f(XIN)/4096 interrupt ! 1, VSYNC interrupt ! 1, BRK interrupt ! 1 2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator) Built-in 32 characters ! 2 lines (maximum 16 lines by software) CC mode: 16 ! 26 dots (character dot structure : 16 ! 20 dots) OSD mode: 16 ! 20 dots 254 kinds CC mode: 1 kinds OSD mode: 8 kinds Maximum 7 kinds (R, G, B) 128 levels (horizontal) ! 512 levels (vertical)
Input/Output ports
ROM RAM OSD ROM OSD RAM P0 P10-P17
I/O I/O
P20-P27
I/O
P30, P31 P50, P51 P52-P57, P6 Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt
I/O Input Output
Clock generating circuit Data slicer OSD function
Number of display characters Character display area Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical)
4
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONS (continued)
Parameter Power source voltage Power dissipation 5 V 10 % Functions
In high-speed OSD ON Data slicer ON 165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz) mode OSD OFF Data slicer OFF 82.5 mW typ. (at oscillation frequency f(XIN) = 8 MHz) In low-speed mode In stop mode OSD OFF Data slicer OFF 0.33mW typ. (at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stopped) 0.055 mW (maximum) -10 C to 70 C CMOS silicon gate process 52-pin shrink plastic molded DIP
Operating temperature range Device structure Package
5
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION
Pin Name Input/ Output Functions Apply voltage of 5 V 10 % (typical) to VCC and AVCC, and 0 V to VSS. Connected to VSS. To enter the reset state, the reset input pin must be kept at a "L" for 2 ms or more (under normal VCC conditions) If more time is needed for the quartz-crystal oscillator to stabilize, this "L" condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. See note 1 at end of Table for full details of port P0 functions. Pins P00-P05 are also used as PWM output pins PWM0-PWM5 respectively. The output structure is N-channel open-drain output. Pins P06 , P07 are also used as external interrupt input pins INT2, INT1 respectively. P06 pin is also used as analog input pin AD4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. P10 pin is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11-P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P15-P17 are also used as analog input pins AD1 to AD3 respectively. P15 pin is also used as external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. When using serial I/O, the output structure is N-channel open-drain output. P22 pin is also used as serial I/O data input pin SIN. P21 pin is also used as serial I/O data output pin SOUT. When using serial I/O, the output structure is N-channel open-drain output. Pins P23, P24 are also used as external clock input pins TIM3, TIM2 respectively. P26 pin is also used as OSD clock input pin OSC1. (See note 2) P27 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. (See note 2) P26 pin is also used as sub-clock input pin XCIN. P27 pin is also used as sub-clock output pin XCOUT. Ports P30, P31 are 2-bit I/O ports and have basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected. (See note 3) Pins P30, P31 are also used as analog input pins AD5, AD6 respectively. VCC, AVCC Power source VSS CNVSS CNVSS ______ RESET Reset input
Input
XIN XOUT P00/PWM0- P05/PWM5, P06/INT2/ AD4, P07/INT1
Clock input Clock output I/O port P0
Input Output I/O
PWM output
Output Input Input I/O Output I/O Input Input I/O I/O
External interrupt input Analog input P10/OUT2, I/O port P1 P11/SCL1, P12/SCL2, OSD output P13/SDA1, P14/SDA2, Multi-master I2C-BUS interface P15/AD1/ INT3, Analog input P16/AD2, External interrupt P17/AD3 input P20/SCLK, I/O port P2 P21/SOUT, P22/SIN, Serial I/O synchroP23/TIM3, nous clock input/ P24/TIM2, output P25, P26/OSC1/ Serial I/O data input XCIN, Serial I/O data P27/OSC2/ output XCOUT External clock input Clock input for OSD Clock output for OSD Sub-clock input Sub-clock output P30/AD5, I/O port P3 P31/AD6 Analog input
Input Output Input Input Output Input Output I/O Input
6
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION (continued)
Pin Name Input/ Output Input Input Input Output Output Functions Ports P50 and P51 are 2-bit input ports. Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD. Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD. Ports P52-P57 are 6-bit output ports. The output structure is CMOS output. Pins P52-P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. Port P6 is an 8-bit output port. The output structure is CMOS output. Input composite video signal through a capacitor. P50/HSYNC Input port P5 P51/VSYNC HSYNC input VSYNC input P52/R, P53/G Output port P5 P54/B OSD output P55/OUT1, P56, P57 P60-P67 CVIN Output port P6 I/O for data slicer
Output Input
Connect a capacitor between VHOLD and VSS. Input VHOLD HLF Connect a filter using of a capacitor and a resistor between HLF and VSS. Notes 1 : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input ("0") or an output ("1"). The pins programmed as "1" in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output "L" voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2 : To switch pin functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set the corresponding bits of the port P2 direction register to "0" (input mode). 3 : To switch output structures, set bits 2 and 3 of the port P3 direction register. When "0," CMOS output ; when "1," N-channel open-drain output.
7
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Ports P00-P05 Direction register
N-channel open-drain output Ports P00-P05
Data bus
Port latch
Note: Each port is also used as follows: P00 -P05 ; PWM0-PWM5
Ports P1, P2, P30, P31 Direction register
CMOS output
Data bus Port latch
Ports P1, P2, P30, P31 Note: Each port is also used as follows: P20 : SCLK P10 : OUT2 P11 : SCL1 P21 : SOUT P12 : SCL2 P22 : SIN P13 : SDA1 P23 : TIM3 P24 : TIM2 P14 : SDA2 P15 : AD1/INT3 P30 : AD5 P16 : AD2 P31 : AD6 P17 : AD3
Ports P06, P07 Direction register
N-channel open-drain output Ports P06, P07
Data bus
Port latch
Note: Each port is also used as follows: P06 : INT2/AD4 P07 : INT1
Fig. 1. I/O Pin Block Diagram (1)
8
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
P50, P51
P52-P57, P6
CMOS input
CMOS output
Internal circuit
P50, P51 Internal circuit P52-P57, P6
Note: Each pin is also used as follows: P50 : HSYNC P51 : VSYNC
Note: Each pin is also used as follows: P52 : R P53 : G P54 : B P55 : OUT1
Fig. 2. I/O Pin Block Diagram (2)
9
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The M37273MF-XXXSP uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00 CPU mode register (CPUM (CM)) [Address FB16] Name 0, 1 Processor mode bits (CM0, CM1) B Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW
2
Stack page selection bit (CM2) (See note)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (X IN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN-XOUT selected (high-speed mode) 1: XCIN-XCOUT selected (high-speed mode)
1 0
0
RW
Note: This bit is set to "1" after the reset release.
Fig. 3. CPU Mode Register
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MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MEMORY Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage, for stack area of subroutine calls and interrupts, and for ROM memory for correction.
ROM
ROM is used for storing user programs as well as the interrupt vector area.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
RAM for OSD
RAM for display is used for specifying the character codes and colors to display.
ROM for OSD
ROM for display is used for storing character data.
ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 033F16 06FF16 Not used RAM for OSD (Note) (128 bytes) 080016 087F16 100016 ROM for OSD (10K bytes) Not used Zero page SFR1 area
1000016
RAM (1472 bytes)
SFR2 area Not used ROM correction memory (RAM) Block 1: addresses 0300 16 to 031F16 Block 2: addresses 0320 16 to 033F16 Not used
1140016 13BFF16
ROM (60K bytes)
Not used
FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16
Note : Refer to table 10. contents of RAM for OSD.
Fig. 4. Memory Map
11
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR1 Area (addresses C016 to DF16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
b7
Bit allocation
b0 b7
State immediately after reset ? 0016 ? 0016 ? 0016 00 0016 ? ? ? 0016 0016 ? ? ? 0016 0016 ? ? ? ? ? ? 4016 0016 ? ? 0016 0016 0016 0016
b0
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3)
T3SC P31 P30 P31C P30C P31D P30D
0
0
0
0
?
?
Port P5 (P5) OSD port control register (PF) Port P6 (P6) Caption data register 3 (CD3) Caption data register 4 (CD4) OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Vertical position register 1 (VP1) Vertical position register 2 (VP2) Window register 1 (WN1) Window register 2 (WN2) I/O polarity control register (PC) Raster color register (RC) PF7
PF5 PF4 PF3 PF2
0
0
CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20 CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
0
OC6 OC5 OC4 OC3 OC2 OC1 OC0 HP6 HP5 HP4 HP3 HP2 HP1 HP0
BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 WN17 WN16 WN15 WN14 WN13 WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23 WN22 WN21 WN20
0
RC7
PC6 PC5 PC4 PC3 PC2 PC1 PC0
0
0
RC4 RC3 RC2 RC1 RC0
Interrupt input polarity control register (RE)
INT3 INT2 INT1
0016 0016 0016
Fig. 5. Memory Map of Special Function Register 1 (SFR1) (1)
12
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR1 Area (addresses E016 to FF16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address
Register
b7
Bit allocation 1 0 1 0 0 1
b0 b7
DSC20
State immediately after reset 0 ? 0016 0? 0016 0016 0016 01 00 0016 0016 0016 ? 0016 ?0 0016 0716 FF16 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 11 0016 0016 0016 0016 ? 0
b0
E016 Data slicer control register 1 (DSC1) 0 E116 Data slicer control register 2 (DSC2) E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Caption data register 1 (CD1) Caption data register 2 (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register 2 Data slicer test register 1 Synchronous signal counter register (HC) Serial I/O register (SIO) Serial I/O mode register (SM) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 5 (T5) Timer 6 (T6) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) address register (S0D) I2C status register (S1) control register (S1D) I2C clock control register (S2) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) I2 C I2 C
DSC12 DSC11 DSC10
DSC25 DSC24 DSC23
?
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10 CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
0
1
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0 0
0 0
0 ?
0 0
0 0
1 0
HC5 HC4 HC3 HC2 HC1 HC0
0
SM6 SM5
0
ADC14
SM3 SM2 SM1 SM0
ADC12 ADC11 ADC10
0
0
0
0
0
0
ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB
0
0
0
0
0
?
10BIT BSEL1 BSEL0 ALS ESO BC2 BC1 BC0 SAD ACK FAST ACK CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
CM7 CM6 CM5
1
1
CM2
0
0
0
0
1
1
0
0
IN3R VSCR OSDR TM4R TM3R TM2R TM1R
0
TM56R IICR IN2R CKR SIR DSR IN1R CK0
IN3E VSCE OSDE TM4E TM3E TM2E TM1E
TM56C TM56E IICE IN2E CKE SIE DSE IN1E
Fig. 6. Memory Map of Special Function Register 1 (SFR1) (2)
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MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR2 Area (addresses 20016 to 20F16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16
Register
b7
Bit allocation
b0 b7
State immediately after reset ? ? ? ? ? ? ? ?
b0
PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5)
0016 0016
PWM mode register 1 (PM1) PWM mode register 2 (PM2) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)
PM13 PM10
?
?
?
0
0
PM25 PM24 PM23 PM22 PM21 PM20
ADH17 ADH16 ADH15 ADH14 ADH13 ADH12 ADH11 ADH10 ADL17 ADL16 ADL15 ADL14 ADL13 ADL12 ADL11 ADL10 ADH27 ADH26 ADH25 ADH24 ADH23 ADH22 ADH21 ADH20 ADL27 ADL26 ADL25 ADL24 ADL23 ADL22 ADL21 ADL20
RC1 RC0
?0 0016 ? ? ? ? 0016 ?
?
?
0
Fig. 7. Memory Map of Special Function Register 2 (SFR2) (1)

0 : "0" immediately after reset
:
Name
:
Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation
b0 b7
State immediately after reset
b0
N
V
T
B
D
I
Z
C
?????1?? Contents of address FFFF16 Contents of address FFFE16
Fig. 8. Internal State of Processor Status Register and Program Counter at Reset
14
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 17 different sources consisting of 4 external, 11 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status register are automatically stored into the stack. (2) The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." (3) The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 10 to 14 shows the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1," interrupt request bit is "1," and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 10 shows interrupt control.
Interrupt Causes
(1) VSYNC and OSD Interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2, INT3 Interrupts With an external interrupt input, the system detects that the level of a pin changes from "L" to "H" or from "H" to "L," and generates an interrupt request. The input active edge can be selected by bits 0, 1 and 2 of the interrupt input polarity register (address 00DC16) : when this bit is "0," a change from "L" to "H" is detected; when it is "1," a change from "H" to "L" is detected. Note that all bits are cleared to "0" at reset. (3) Timer 1, 2, 3 and 4 Interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) Serial I/O Interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 Interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Clear bit 0 of the PWM mode register 1 to "0." (6) Data slicer Interrupt An interrupt occurs when slicing data is completed. (7) Multi-master I2C-BUS Interface Interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (8) Timer 5 * 6 Interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (9) BRK Instruction Interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Table 1. Interrupt Vector Addresses and Priority Interrupt Source Reset OSD interrupt INT1 interrupt Data slicer interrupt Serial I/O interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt INT3 interrupt INT2 interrupt Multi-master I2C-BUS interface interrupt Timer 5 * 6 interrupt BRK instruction interrupt Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Source switch by software (Note) Non-maskable (software interrupt) Active edge selectable Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks
Note : Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
15
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt request bit Interrupt enable bit
Interrupt disable flag I
BRK instruction Reset
Interrupt request
Fig. 9. Interrupt Control
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC 16] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV R--
0 : No interrupt request issued Timer 1 interrupt 1 : Interrupt request issued request bit (TM1R) Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 3 interrupt 1 : Interrupt request issued request bit (TM3R) 0 : No interrupt request issued Timer 4 interrupt 1 : Interrupt request issued request bit (TM4R) OSD interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit (OSDR) 0 : No interrupt request issued VSYNC interrupt request bit (VSCR) 1 : Interrupt request issued INT3 interrupt request 0 : No interrupt request issued bit (VSCR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
V: "0" can be set by software, but "1" cannot be set.
Fig. 10. Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV RW
INT1 interrupt request bit (INIR) 1 Data slicer interrupt request bit (DSR) 2 Serial I/O interrupt request bit (S1R) 3 f(XIN)/4096 interrupt request bit (CKR) 4 INT2 interrupt request bit (IN2R) 5 Multi-master I 2C-BUS interrupt request bit (IICR) 6 7 Timer 5 * 6 interrupt request bit (TM56R) Fix this bit to "0."
V: "0" can be set by software, but "1" cannot be set.
Fig. 11. Interrupt Request Register 2
16
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 1 2 3 4 5 6 7 Name Timer 1 interrupt enable bit (TM1E) Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt enable bit (TM3E) Timer 4 interrupt enable bit (TM4E) OSD interrupt enable bit (OSDE) VSYNC interrupt enable bit (VSCE) INT3 interrupt enable bit (IN3E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Fig. 12. Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 5 6 7 Name INT1 interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (SIE) f(XIN)/4096 interrupt enable bit (CKE) INT2 interrupt enable bit (IN2E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Multi-master I 2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled Timer 5 * 6 interrupt enable bit (TM56E) Timer 5 * 6 interrupt switch bit (TM56C) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6
Fig. 13. Interrupt Control Register 2
17
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC16]
B 0 1 2 3 to 7
Name INT1 polarity switch bit (INT1) INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3)
Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
After reset 0 0 0 0
RW RW RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 14. Interrupt Input Polarity Register
18
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37273MF-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 17. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse, after the count value reaches "0016".
(5) Timer 5
Timer 5 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 2 overflow signal Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of the timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow.
* * *
(6) Timer 6 (1) Timer 1
Timer 1 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/4096 or f(XCIN)/4096 External clock from the TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow.
* * *
Timer 6 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow.
* *
(2) Timer 2
Timer 2 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 1 overflow signal External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
* * *
(3) Timer 3
Timer 3 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XCIN) External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow.
* * *
At reset, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. The f(XIN) V /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. However, the f(XIN) V /16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to "0" before the execution of the STP instruction (f(XIN) V /16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. V : When bit 7 of the CPU mode register (CM7) is "1," f(XIN) becomes f(XCIN). The timer-related registers is shown in Figure 15 and 16.
(4) Timer 4
Timer 4 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/2 or f(XCIN)/2 f(XCIN) The count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
* * *
19
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B Name 0 Timer 1 count source selection bit 1 (TM10) 1 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) Functions After reset R W 0: f(XIN)/16 or f(XCIN)/16 (Note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow 0 RW
2 3 4
0 0 0
RW RW RW
5
0
RW
6 7
0 0
RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 15. Timer Mode Register 1
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C716) b0 0 0 : f(XIN)/16 or f(XCIN)/16 (See note) 0 1 : f(XCIN) 1 0: External clock from TIM3 pin 1 1: b4 0 0 1 1 b1 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XIN)/2 or f(XCIN)/2 (See note) 1 : f(XCIN) After reset R W 0 RW
1, 4 Timer 4 count source selection bits (TM21, TM24)
0
RW
2 3 5 6 7
Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 6 of TM1
0 0 0 0 0
RW RW RW RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Fig. 16. Timer Mode Register 2
20
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
XCIN
CM7 TM15 1/4096 Timer 1 latch (8)
8
XIN
1/2
1/8
TM10 TM12 TM14
Timer 1 (8)
8 8
Timer 1 interrupt request
Timer 2 latch (8)
8
TIM2 TM11 TM13
Timer 2 (8) 8
8
Timer 2 interrupt request
FF16 T3SC Timer 3 latch (8)
8
Reset STP instruction
TIM3 TM20 TM22
Timer 3 (8) 8
8
Timer 3 interrupt request
TM21
0716 Timer 4 latch (8)
8
Timer 4 (8) TM21 TM24 TM23 TM16 Selection gate : Connected to black side at reset TM1 : Timer mode register 1 TM2 : Timer mode register 2 T3SC : Timer 3 count source switch bit (address 00C7 16) CM : CPU mode register TM27 TM25 8
8
Timer 4 interrupt request
Timer 5 latch (8)
8
Timer 5 (8) 8
8
Timer 5 interrupt request
Timer 6 latch (8)
8
Timer 6 (8) TM17 TM26 8
Timer 6 interrupt request
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 17. Timer Block Diagram
21
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
SERIAL I/O
The M37273MF-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 18. The synchronous clock I/O pin (SCLK), and data output pin (SOUT), data input pin (SIN) also functions as port P20, P21, P22 respectively. Bit 2 of the serial I/O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT, SCLK, and SIN pins for serial I/O, set the corresponding bits of the port P2 direction register to "0."
The operation of the serial I/O is described below. The operation differs depending on the clock source; external clock or internal clock.
XCIN 1/2 XIN 1/2 CM7
Synchronous circuit
Data bus 1/2 Frequency divider
1/2 1/4 1/8 1/16
SM2
S
SM1 SM0
Selection gate: Connect to black side at reset.
P20 Latch SCLK SM3 P21 Latch SOUT SIN SM6 SM3 SM5 : LSB MSB (Note) Serial I/O shift register (8) 8 Serial I/O counter (8)
CM : CPU mode register SM : Serial I/O mode register Serial I/O interrupt request
Note : When the data is set in the serial I/O register (address 00EA 16), the register functions as the serial I/O shift register.
Fig. 18. Serial I/O Block Diagram
22
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Internal clock: The serial I/O counter is set to "7" during the write cycle into the serial I/O register (address 00EA16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes "0" and the transfer clock stops at HIGH. At this time the interrupt request bit is set to "1." External clock: When an external clock is selected as the clock source, the interrupt request is set to "1" after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 500kHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 19. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input leve is HIGHl.
Synchronous clock
Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7
Interrupt request bit is set to "1" Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed.
Fig. 19. Serial I/O Timing (for LSB first)
23
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Serial I/O mode register (SM) [Address 00EB16] B Name b1 0 0 1 1 Functions b0 0: f(XIN)/4 or f(XCIN)/4 1: f(XIN)/16 or f(XCIN)/16 0: f(XIN)/32 or f(XCIN)/32 1: f(XIN)/64 or f(XCIN)/64 After reset R W RW 0
0, 1 Internal synchronous clock selection bits (SM0, SM1)
2 3
Synchronous clock selection bit (SM2) Port function selection bit (SM3)
0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT
0
RW
0
RW
4, 7 Fix these bits to "0." 5 6 Transfer direction selection bit (SM5) 0: LSB first 1: MSB first
0 0 0
RW RW RW
0: Input signal from S IN pin Transfer clock input pin selection bit (SM6) 1: Input signal from S OUT pin
Fig. 20. Serial I/O Mode Register
24
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PWM OUTPUT FUNCTION
The M37273MF-XXXSP is equipped with six 8-bit PWMs (PWM0-PWM5). PWM0-PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s (for f(XIN) = 8 MHz) and repeat period of 1024 s (for f(XIN) = 8 MHz). Figure 21 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0-PWM5 using f(XIN) divided by 2 as a reference signal.
(1) Data Setting
When outputting PWM0-PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 020016 to 020516).
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register.
(3) Operating of 8-bit PWM
The following explains PWM operation. First, set the bit 0 of PWM mode register 1 (address 020816) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0-PWM5 are also used as pins P00-P05. Set the corresponding bits of the port P0 direction register to "1" (output mode). And select each output polarity by bit 3 of PWM mode register 1 (address 020816). Then, set bits 5 to 0 of PWM mode register 2 (address 020916) to "1" (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 22 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 22 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 22 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH cannot be output, i.e. 256/256.
(4) Output after Reset
At reset, the output of ports P00-P05 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
25
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data bus XIN 1/2 PM10 PWM0 register (Address 020016) b7
8
PWM timing generating circuit
b0
PM13 8-bit PWM circuit
P00 PM20 P01 PM21 P02 PM22 P03 PM23 P04 PM24 P05 PM25
D00
PWM0
D01
PWM1
PWM1 register (Address 0201 16)
D02
PWM2
PWM2 register (Address 0202 16)
D03
PWM3
PWM3 register (Address 0203 16)
D04
PWM4
PWM4 register (Address 0204 16)
D05
PWM5
PWM5 register (Address 0205 16)
Selection gate : Connected to black side at reset. Inside of is as same contents with the others.
PM1 : PWM mode register 1 ( address 020816) PM2 : PWM mode register 2 ( address 020916) P0 : Port P0 register (address 00C016) D0 : Port P0 direction register ( address 00C116)
Fig. 21. PWM Block Diagram
26
13579 50 60 70
20
30
40
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250 255
Bit 7
50 54 62 66 70 74 86 90 94 58 78 82 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
Fig. 22. 8-bit PWM Timing
52 60 76 228 84 188 116 148 180 220 236 212 68 172 92 100 244 108 124 164 204 132 140 156 196 252 56 104 184 136 216 72 88 168 120 200 152 232 248 80 144 176 208 112 240 96 160 224 64 192 128
2
6
10
14
18
22
26
30
34
38
42
46
Bit 6
4
12
20
28
36
44
Bit 5
8
24
40
Bit 4
16
48
Bit 3
32
Bit 2
Bit 1
Bit 0
(a) Pulses showing the weight of each bit
0016 (0)
0116 (1)
1816 (24)
FF16 (255)
t T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
27
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PM1) [Address 020816] B 0 Name PWM counts source selection bit (PM10) Functions 0 : Count source supply 1 : Count source stop After reset 0 RW RW
1, 2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- 4 to 7 When these bits are read out, the values are "0." 3 PWM output polarity selection bit (PM13) 0 : Positive polarity 1 : Negative polarity 0 RW
Fig. 23. PWM Mode Register 1
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 00 PWM mode register 2 (PM2) [Address 020916] B Name 0 P00/PWM0 output selection bit (PM20) 1 2 3 4 5 P01/PWM1 output selection bit (PM21) P02/PWM2 output selection bit (PM22) P03/PWM3 output selection bit (PM23) P04/PWM4 output selection bit (PM24) P05/PWM5 output selection bit (PW25) Functions 0 : P00 output 1 : PWM0 output 0 : P01 output 1 : PWM1 output 0 : P02 output 1 : PWM2 output 0 : P03 output 1 : PWM3 output 0 : P04 output 1 : PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 RW RW RW RW RW RW
6, 7 Fix these bits to "0."
Fig. 24. PWM Mode Register 2
28
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D COMPARATOR
A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 25. The reference voltage "Vref" for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00ED16). The comparison result of the analog input voltage and the reference voltage "Vref" is stored in bit 4 of the A-D control register (address 00EC16).
For A-D comparison, set "0" to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8).
Data bus
A-D control register 1
Bits 0 to 2
Comparator control
AD1 AD2 AD3 AD4 AD5 AD6
A-D control register 1 Analog signal switch Comparator Bit 4 Bit 5 Bit 4
A-D control register 2 Bit 3 Bit 2 Bit 1 Bit 0
Switch tree
Resistor ladder
Fig. 25. A-D Comparator Block Diagram
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16]
B
0 to 2
Name
Analog input pin selection bits (ADC10 to ADC12) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0: Do not set. 1:
After reset R W
0
RW
3, Nothing is assigned. This bits are write disable bits. 5 to 7 When these bits are read out, the values are "0." 0: Input voltage < reference voltage 4 Storage bit of comparison result (ADM4) 1: Input voltage > reference voltage
0 Indeterminate
R-- RW
Fig. 26. A-D Control Register 1
29
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED16]
B 0 to 5
Name D-A converter set bits (ADC20 to ADC25)
Functions
Reference voltage b5 b4 b3 b2 b1 b0 Vref
After reset 0
RW RW
0 0 0 1 1 1
0 0 0 1 1 1
0 0 0 1 1 1
0 0 0 1 1 1
0 0 1 0 1 1
0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0."
Fig. 27. A-D Control Register 2
30
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
DATA SLICER
The M37273MF-XXXSP includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip's polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00E016) to "0." These settings can realize the low-power dissipation.
Composite video signal
0.1 F 1M
470 560 pF 1 F
1k 200 pF Sync pulse counter register (address 00E916) HLF
CVIN
HSYNC
Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit
Synchronizing separation circuit
Data slicer control register 2 (address 00E116)
Data slicer control register 1 (address 00E016) Timing signal generating circuit
Data slicer ON/OFF
Reference voltage generating 1000 pF circuit
VHOLD
+ - Comparator
Clock run-in determination circuit
Data slice line specification circuit
Clock run-in defect register (address 00E4 16)
Start bit detecting circuit
External circuit Note : Make the length of wiring which is connected to VHOLD, HLF, and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
Caption position register (address 00E616)
Data clock generating circuit Data clock position register (address 00E516) 16-bit shift register Interrupt request generating circuit
high-order low-order Caption data register 1 (address 00E216)
Data slicer interrupt request
Caption data register 2 (address 00E316)
Caption data register 4 (address 00CF16)
Caption data register 3 (address 00CE16)
Data bus
Fig. 28. Data Slicer Block Diagram
31
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is "0," terminate the pins as shown in Figure 29.

Apply the same voltage as VCC to AVCC pin. Leave HLF pin open. Open Open
19
AVCC HLF VHOLD CVIN
20
Leave VHOLD pin open. Pull-down CV IN pin to VSS through a resistor of 5 k or more.
21
5k
or more
22
Fig. 29. Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State When both bits 0 and 2 of data slicer control register 1 (address 00E016) are "1," terminate the pins as shown in Figure 30.

Apply the same voltage as V CC to AVCC pin.
19 1k
AVCC HLF
Connect the same external circuit as when using data slicer to HLF pin. Leave VHOLD pin open. Pull-up CVIN to VCC through a resistor of 5 k or more.
20 1 F 200pF
Open
21
VHOLD
5k
or more
22
CVIN
Fig. 30. Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
32
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Figure 31 shows the structure of the data slicer control registers.
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 01100 Data slicer control register 1(DSC1) [Address 00E016] B 0 Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 0 RW RW RW RW RW
Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3, 4, Fix these bits to "0." 7 5, 6 Fix these bits to "1."
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 31. Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 1 Data slicer control register 2 (DSC2) [Address 00E116]
B 0
Name Caption data latch completion flag 1 (DSC20)
Functions
After reset
RW
Indeterminate R -- 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) RW
1
Fix this bit to "1."
2, 7 Test bit 3 4 Field determination flag (DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24)
Indeterminate R -- Indeterminate R -- 0 RW
5 6
0: Match V-pulse shape determination flag (DSC25) 1: Mismatch Fix this bit to "o."
Indeterminate R -- 0 RW
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Fig. 32. Data Slicer Control Register 2
33
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video signal is input requires a capacitor (0.1 mF) coupling outside. Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition, we recommend to install externally a simple lowpass filter using a resistor and a capacitor at the CVIN pin (refer to Figure 28).
Composite sync signal Measure "L" period Timing signal
(3) Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
Vsep signal
(4) Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. Horizontal Synchronous Signal (Hsep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. Vertical Synchronous Signal (Vsep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00E116). *Method 1 The "L" level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this "L" level. *Method 2 The "L" level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the "L" level period of the timing signal immediately after this "L" level. If a falling exists, a Vsep signal is generated in synchronization with the rising of the timing signal (refer to Figure 33). Figure 33 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 34, when the A level matches the B level, this bit is "0." In the case of a mismatch, the bit is "1."
A Vsep signal is generated at a rising of the timing signal immediately after the "L" level width of the composite sync signal exceeds a certain time.
Fig. 33. Vsep Generating Timing (method 2)
34
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 00E016) to "1." The reference clock can be used as a display clock for OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00E016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 28. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming.
Bit 5 of DSC2 0 Composite sync signal 1 1 A B
Fig. 34. Determination of V-pulse Waveform
35
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) Data Slice Line Specification Circuit
Specification of Data Slice Line This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their data. The caption position register (address 00E616) is used for each setting (refer to Table 3). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is sliced. The values of "0016" to "1F16" can be set in the caption position register (at setting only 1 appropriate line). Figure 35 shows the signals in the vertical blanking interval. Figure 36 shows the structure of the caption position register. Specification of Line to Set Slice Voltage The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to Table 2). The field to generate slice voltage is specified by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to Table 2). Field Determination The field determination flag can be read out by bit 3 of data slicer control register 2. This flag charge at the falling edge of Vsep.
Video signal
Vertical blanking interval
Composite video signal Vsep
1 appropriate line is set by the caption position register Line 21 (when setting line 19)
Hsep
Count value to be set in the caption position register ("0F 16" in this case)
Magnified drawing
Hsep Clock run-in Start bit + 16-bit data
Composite video signal Window for deteminating clock-run-in
Start bit
Fig. 35. Signals in Vertical Blanking Interval
36
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616]
B 0 to 4 5
Name Caption position bits (CPS0 to CPS4) Caption data latch completion flag 2 (CPS1)
Functions
After reset 0
RW RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (P33). 0 RW
6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7)
Fig. 36. Caption Position Register
Table 2. Specification of Data Slice Line CPS b7 0 b6 0 Field and Line to Be Sliced Data * Both fields of F1 and F2 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) * Both fields of F1 and F2 * A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) * Both fields of F1 and F2 * Line 21 (total 1 line) * Both fields of F1 and F2 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) Field and Line to Generate Slice Voltage * Field specified by bit 1 of DSC1 * Line 21 (total 1 line) * Field specified by bit 1 of DSC1 * A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) * Field specified by bit 1 of DSC1 * Line 21 (total 1 line) * Field specified by bit 1 of DSC1 * Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2)
0 1 1
1 0 1
Notes 1: DSC is data slicer control register 1. CPS is caption position register. 2: Set "0016" to "1D16" to bits 4 to 0 of CPS. 3: Set "0016" to "1F16" to bits 4 to 0 of CPS.
37
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(7) Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. Reference Voltage Generating Circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
(8) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line specification circuit. The detection of a start bit is described below. A sampling clock is generated by dividing the reference clock output by the timing signal. A clock run-in pulse is detected by the sampling clock. After detection of the pulse, a start bit pattern is detected from the comparator output.
(9) Clock run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. The reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00E416). Read out these bits after the occurrence of a data slicer interrupt (refer to (12) Interrupt Request Generating Circuit). Figure 37 shows the structure of clock run-in detect register.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E4 16] B 0 to 2 3 to 7 Test bits Name Read-only Functions After reset R W 0 R--
Clock run-in detection bit (CRD3 to CRD7)
Number of reference clocks to be counted in one clock run-in pulse period.
0
R--
Fig. 37. Clock Run-in Detect Register
38
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Data clock generating circuit
This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores caption data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 Data clock position register (DPS) [Address 00E516]
B 0 2 1 3 4 to 7
Name Fix these bits to "0." Fix this bit to "1." Data clock position set bits (DPS3 to DPS7)
Functions
After reset R W 1 0 0 1 0 RW RW RW
Fig. 38. Data Clock Position Register
39
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(11) 16-bit Shift Register
The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00E316) and data register 4 (address 00CF16). The contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00E216) and data register 3 (address 00CE16), respectively. These registers are reset to "0" at a falling of Vsep. Read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to (12) Interrupt Request Generating Circuit).
(12) Interrupt Request Generating Circuit
The interrupt requests as shown in Table 4 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00E616). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request.
Table 3. Contents of Caption Data Latch Completion Flag and 16-bit Shift Register Slice Line Specification Mode CPS bit 7 0 0 1 1 bit 6 0 1 0 1 Contents of Caption Data Latch Completion Flag Completion Flag 1 (bit 0 of DSC2) Line 21 A line specified by bits 4 to 0 of CPS Line 21 Line 21 Completion Flag 2 (bit 5 of CPS) A line specified by bits 4 to 0 of CPS Invalid Invalid A line specified by bits 4 to 0 of CPS Contents of 16-bit Shift Register Caption Data Registers 1, 2 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of CPS 16-bit data of line 21 16-bit data of line 21 Caption Data Registers 3, 4 16-bit data of a line specified by bits 4 to 0 of CPS Invalid Invalid 16-bit data of a line specified by bits 4 to 0 of CPS
CPS: Caption position register DSC2: Data slicer control register 2
Table 4. Occurence Sources of Interrupt Request CPS b7 0 1 b6 0 1 0 1 Occurence Souces of Interrupt Request at End of Data Slice Line After slicing line 21 After a line specified by bits 4 to 0 of CPS After slicing line 21 After slicing line 21
CPS: Caption position register
40
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(13) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds "1F16," "1F16" is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter register (address 00E916). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 020816). Figure 39 shows the structure of the sync pulse counter and Figure 40 shows the synchronous signal counter block diagram.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916]
B 0 to 4 5
Name Count value (HC0 to HC4)
Functions
After reset 0
RW R--
Count source (HC5)
0: HSYNC signal 1: Composite sync signal f(XIN )/213 (1024 s, f(X IN) = 8 MHz)
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Fig. 39. Sync Pulse Counter Register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
b5
Latch (5 bits)
Sync pulse counter register
Selection gate : connected to black side when reset.
Data bus
Fig. 40. Synchronous Signal Counter Block Diagram
41
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 41 shows a block diagram of the multi-master I2C-BUS interface and Table 5 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits.
Table 5. Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
: System clock = f(XIN)/2 Note: We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
b7
I2C address register (S0D)
b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
b7
I 2 C data shift register S0
b0 b7
MST TRX BB PIN
b0
AL AAS AD0 LRB
AL circuit
Internal data bus
I 2 C status register (S1)
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
b7
BSEL1 BSEL0 10BIT SAD ALS
b0
ESO BC2 BC1 BC0
I2 C clock control register (S2) Clock division
I2C clock control register (S1D) System clock ( ) Bit counter
Fig. 41. Block Diagram of Multi-master I2C-BUS Interface
42
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
Fig. 42. I2C Data Shift Register
43
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. ____ s Bit 0: Read/Write Bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. s Bits 1 to 7: Slave Address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616]
2
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
After reset
RW
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Fig. 43. I2C Address Register
44
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(3) I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. s Bits 0 to 4: SCL Frequency Control Bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 7. s Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set. s Bit 6: ACK Bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to "0," the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). VACK clock: Clock for acknowledgment
s Bit 7: ACK Clock Bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I 2C clock generator is reset, so that data cannot be transmitted normally.
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2) [Address 00FA 16]
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4-CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
...
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock
RW RW RW
6 7
0 0
Note: At 4000kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Fig. 44. I2C Clock Control Register
45
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) I2C Control Register
The I2C control register (address 00F916) controls the data communication format. s Bits 0 to 2: Bit Counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. s Bit 3: I2C Interface Use Enable Bit (ESO) This bit enables usage of the multi-master I2C BUS interface. When this bit is set to "0," the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ESO = "0," the following is performed. PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00F816 ). Writing data to the I2C data shift register (address 00F616) is disabled. s Bit 5: Addressing Format Selection Bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. s Bits 6 and 7: Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 45).
"0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14
* *
s Bit 4: Data Format Selection Bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "(5) I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized.
Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 021316) to "1." Moreover, set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface. Fig. 45. Connection Port Control by BSEL0 and BSEL1
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00F916]
B
0 to 2
Name
Bit counter (Number of transmit/receive bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0: 1: 0: 1: 0: 1: 0: 1:
Functions
8 7 6 5 4 3 2 1
After reset R W
0
RW
3 4 5
I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD)
0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports
Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output.
Fig. 46. I2C Control Register
46
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) I2C Status Register
The status register (address 00F816) controls the interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. s Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). s Bit 1: General Call Detecting Flag (AD0) This bit is set to "1" when a general callV whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address "0016" to all slaves. s Bit 2: Slave Address Comparison Flag (AAS) This flag indicates a comparison result of address data. In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions. The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). A general call is received. In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition. When the address data is compared with the I 2C address register (8 bits consists of slave address and RBW), the first bytes match. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). s Bit 3: Arbitration LostV Detecting Flag (AL) In the master transmission mode, when a device other than the microcomputer sets the SDA to "L,", arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. I2C I2C-BUS
* * *
VArbitration lost: The status in which communication as a master is disabled.
s Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to "0" in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 48 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in any one of the following conditions. Executing a write instruction to the I2C data shift register (address 00F616). When the ES0 bit is "0" At reset The conditions in which the PIN bit is set to "0" are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = "1" and immediately after completion of address data reception s Bit 5: Bus Busy Flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ES0 bit of the I2C control register (address 00F916) is "0" and at reset, the BB flag is kept in the "0" state. s Bit 6: Communication Mode Specification Bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is "0" in the slave reception mode is selected, the TRX bit is set to "1" __ (transmit) if the least significant bit (R/W bit) of the address data_ trans_ mitted by the master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurrence of a START condition is disabled by the START condition duplication prevention function (Note). With MST = "0" and when a START condition is detected. With MST = "0" and when ACK non-return is detected. At reset
* * * * * * *
* * * * * *
47
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in one of the following conditions.
* Immediately after completion of 1-byte data transmission when arbitration lost is detected
* When a STOP condition is detected. * When occurrence of a START condition is disabled by the START
condition duplication preventing function (Note).
* At reset
Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: * a START condition is set by another master device.
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave receive mode 1 : Slave transmit mode 0 : Master receive mode 1 : Master transmit mode
After reset R W
Indeterminate 0 0 0 0 0 0
R-- R-- R-- R-- R-- RW RW
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannot be written.
Fig. 47. I2C Status Register
SCL PIN
IICIRQ
Fig. 48. Interrupt Request Signal Generation Timing
48
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 49 for the START condition generation timing diagram, and Table 8 for the START condition/STOP condition generation timing table.
Table 6. START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode High-speed Clock Mode Setup time 5.0 s (20 cycles) 2.5 s (10 cycles) Hold time 5.0 s (20 cycles) 2.5 s (10 cycles) Set/reset time 3.0 s (12 cycles) 1.5 s (6 cycles) for BB flag Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
(9) START/STOP Condition Detect Conditions
I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag
The START/STOP condition detect conditions are shown in Figure 51 and Table 7. Only when the 3 conditions of Table 7 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" is generated to the CPU.
Fig. 49. START Condition Generation Timing Diagram
SCL
SCL release time Setup time Setup time Hold time Hold time
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence: Set "2016" to the I2C status register (S1). Write a transmit data to the I2C data shift register. Set "F016" to the I2C status register (S1) again. ; S1 = 2016 I2C status register I2C data shift register ; S0 = transmit data after restart I2C status register ; S1 = F016
SDA (START condition) SDA (STOP condition)
Fig. 51. START Condition/STOP Condition Detect Timing Diagram
Table 7. START Condition/STOP Condition Detect Conditions
(8) STOP Condition Generation Method
When the ES0 bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 50 for the STOP condition generation timing diagram, and Table 6 for the START condition/STOP condition generation timing table.
High-speed Clock Mode Standard Clock Mode 1.0 s (4 cycles) < SCL 6.5 s (26 cycles) < SCL release time release time 3.25 s (13 cycles) < Setup time 0.5 s (2 cycles) < Setup time 3.25 s (13 cycles) < Hold time 0.5 s (2 cycles) < Hold time Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag
Fig. 50. STOP Condition Generation Timing Diagram
49
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 52, (1) and (2). 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address regis__ ter (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit __ addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to "1" by __ software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 52, (3) and (4). Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). When a START condition is received, an address comparison is made. *When all transmitted addresses are "0" (general call) : AD0 of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. : *When the transmitted addresses match the address set in AAS of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *In the cases other than the above : AD0 and AAS of the I2C status register (address 00F816) are set to "0" and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00F616). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set "0" in the least significant bit. Set "F016" in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs.
50
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
S
Slave address R/W
A
Data
A
Data
A/A
P
7 bits "0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits "1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte
S
A
A
Data
A
Data
A/A
P
7 bits "0" 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits
S
A
A
Sr
Data
A
Data 1 to 8 bits
A
P
7 bits "0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master
Fig. 52. Address Data Communication Format
51
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD FUNCTIONS
Table 8 outlines the OSD functions of the M37273MF-XXXSP. The M37273MF-XXXSP incorporates an OSD circuit of 32 characters ! 2 lines. There are 2 display modes and they are selected by a block unit. The display modes are selected by bits 0 and 1 of block control register i (i = 1 and 2). The features of each mode are described below.
Table 8. Features of Each Display Mode Display Mode Parameter Number of display characters Character display area Kinds of characters Kinds of character sizes Pre-divide ratio (Note) Dot size Attribute Character font coloring Raster coloring Character background coloring OSD output Function Display expansion (multiline display) Auto solid space function Window function Possible 1 kind ! 2 (fixed) 1TC ! 1/2H Smooth italic, under line, flash 1 screen : 7 kinds, Max. 7 kinds (a character unit) Possible (a screen unit, max. 7 kinds) ------------ Possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) R, G, B, OUT1, OUT2 ------------ 16 ! 26 dots 254 kinds 8 kinds ! 2, ! 3 1TC ! 1/2H, 1TC ! 1H, 2TC ! 2H, 3TC ! 3H Border (black) CC Mode (Closed caption mode) 32 characters ! 2 lines 16 ! 20 dots OSD Mode (Border OFF) (On-screen display mode)
Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as "pre-divide ratio" hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to (2) Dote size).
52
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 53 shows the configuration of OSD character. Figure 54 shows the block diagram of the OSD circuit. Figure 55 shows the OSD control register. Figure 56 shows the block control register.
CC mode OSD mode
16 dots 16 dots Blank areaV
26 dots 20 dots
20 dots
Underline area V Blank area V
V : Displayed only in CCD mode.
Fig. 53. Configuration of OSD Character Display Area
53
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock for OSD OSC1 OSC2 HSYNC VSYNC
Data slicer clock
Display oscillation circuit
Control registers for OSD OSD Control circuit OSD control register Horizontal position register Block control registers Vertical registers Window registers I/O polarity control register Raster color register (address 00D016) (address 00D116) (addresses 00D216, 00D316) (addresses 00D416, 00D516) (addresses 00D616, 00D716) (address 00D816) (address 00D916)
RAM for OSD 2 bytes! 32 characters ! 2 lines
ROM for OSD 16 dots ! 20 dots! 254 characters
Shift register 16-bit Output circuit
R
G
B
OUT1
OUT2
Data bus
Fig. 54. Block Diagram of OSD Circuit
54
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 OSD control register (OC) [Address 00D016] B 0 1 2 3 Name OSD control bit (OC0) (See note) Automatic solid space control bit (OC1) Window control bit (OC2) CC mode clock selection bit (OC3) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : OFF 1 : ON 0 : OFF 1 : ON 0 : Data slicer clock 1 : Clock from OSC1 pin 0 : Data slicer clock 1 : Clock from OSC1 pin
b6 b5
After reset R W 0 0 0 0 0 RW RW RW RW RW
4 OSD mode clock selection bit (OC4) 5, 6 OSC1 clock selection bit (OC5, OC6)
0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set.
0
RW
7 Fix this bit to "0."
0
RW
Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC.
Fig. 55. OSD Control Register
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316] B Name
b1 b0
Functions 0 0 1 1
b4
After reset
RW
0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) 2, 3 Dot size selection bits (BCi2, BCi3) (See note 2 and 3) 4 Pre-divide ratio selection bit (BCi4) (See note 2 and 3) 5
Indeterminate R W
0: Display OFF 1: CC mode 0: OSD mode (Border OFF) 1: OSD mode (Border ON)
b3 0 0 1 1 0 0 1 1 b2 0 1 0 1 0 1 0 1 Pre-divide Ratio Dot Size 1Tc 1Tc 2Tc 3Tc 1Tc 1Tc 2Tc 3Tc ! 1/2H ! 1H ! 2H ! 3H ! 1/2H ! 1H ! 2H ! 3H
Indeterminate R W
0
!2
Indeterminate R W
1
!3
OUT1/OUT2 output 0: OUT1 output control 1: OUT2 output control control bit (BCi5) (See note 1) Vertical display start position control bit (BCi6) Window top/bottom boundary control bit (BCi7) BC16: Block 1 BC26: Block 1 BC17: Window top boundary BC27: Window bottom boundary
Indeterminate R W
6
Indeterminate R W
7
Indeterminate R W
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is "0." Bit RA3 of OSD RAM controls OUT2 output when bit 5 is "1." 2: Tc : OSD clock cycle divided in the pre-divide circuit 3: H : H SYNC
Fig. 56. Block Control Registers
55
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) Display Position
The display positions of characters are specified in units called a "block." There are 2 blocks, blocks 1 and 2. Up to 32 characters can be displayed in each block (refer to (5) Memory for OSD). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 128-step display positions in units of 4 TOSC (TOSC = OSD oscillation cycle). The display position in the vertical direction for each block can be selected from 512-step display positions in units of 1 TH ( TH = HSYNC cycle).
Blocks are displayed in conformance with the following rules: When the display position of block 1 is overlapped with that of block 2 (Figure 57, (b)), the block 1 is displayed on the front. When another block display position appears while one block is displayed (Figure 57, (c)), the block with a larger set value as the vertical display start position is displayed.
(HP) VP1 Block 1 VP2 Block 2 (a) Example when each block is separated
(HP) VP1 = VP2 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1
(HP) VP1 VP2 Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1
Note: VP1 or VP2 indicates the vertical display start position of display block 1 or 2.
Fig. 57. Display Position
56
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/ O polarity control register (address 00D816).
8 machine cycles or more VSYNC signal input 0.25 to 0.50 [s] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal (Note 2) HSYNC signal input 8 machine cycles or more 1 2 3 4 5
Not count When bits 0 and 1 of the I/O polarity control register (address 00D816) are set to "1" (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of H SYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of H SYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more.
Fig. 58. Supplement Explanation for Display Position
57
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The vertical position for each block can be set in 512 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "FF16" in vertical position register i (i = 1 and 2) (addresses 00D416 and 00D516) and values "0" or "1" in bit 6 of block control register i (i = 1 and 2) (addresses 00D216 and 00D316). The structure of the vertical position registers is shown in Figure 59.
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Functions After reset RW
0 Control bits of vertical to display start positions 7 (VPi0 to VPi7) (See note)
Vertical display start positions Indeterminate R W (low-order 8 bits) TH ! (setting value of BCi6 ! 162 + setting value of low-order 4 bits of VPi ! 161 + setting value of low-order 4 bits of VPi ! 160)
Note: Set values except "00 16" to VPi when BCi6 is "0."
Fig. 59. Vertical Position Registers The horizontal position is common to all blocks, and can be set in 128 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle for display) as values "0016" to "FF16" in bits 0 to 6 of the horizontal position register (address 00D116). The structure of the horizontal position register is shown in Figure 60.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00D116] Functions Horizontal display start positions 0 Control bits of horizontal 128 steps (0016 to 7F16) to display start positions 6 (HP0 to HP6) (1 step is 4TOSC) 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Note: The setting value synchronizes with the V SYNC. B Name After reset R W 0 RW
0
R--
Fig. 60. Horizontal Position Register
58
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different predivide ratios, their horizontal display start position will not match. 2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match.
3 : When setting "0016" to the horizontal position register, it needs approximately 62TOSC (= Tdef) interval from a rising edge (when negative polarity is selected) of HSYNC signal to the horizontal display start position.
HSYNC Note 1 Tdef 4TOSC ! N 1TC
Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1TC
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
Tdef'
Note 2
4TOSC' ! N
1TC
Block 4 (Pre-divide ratio = 3, clock source = OSC1)
N 1Tc TOSC Tdef : Value of horizontal position register (decimal notation) : OSD clock cycle divided in the pre-divide circuit : OSD oscillation cycle : 62 TOSC
Fig. 61. Notes on Horizontal Display Start Position
59
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of each block is specified by bits 2 to 4 of the block control register i. Refer to Figure 56 (the structure of the block control register i). The block diagram of dot size control circuit is shown in Figure 62.
OSC1
Synchronous
circuit
"0" Cycle ! 2
Clock cycle = 1TC
Data slicer clock
OC3 or OC4
"1" BCi4 Cycle ! 3
Horizontal dot size control circuit
Pre-divide circuit HSYNC Vertical dot size control circuit
OSD control circuit
Fig. 62. Block Diagram of Dot Size Control Circuit
1 dot
1TC 1/2H 1H
1TC
2TC
3TC Scanning line of F1(F2) Scanning line of F2(F1) 3H
2H
Fig. 63. Definition of Dot Sizes
60
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(3) Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 3 types. Data slicer clock output from the data slicer (approximately 26 MHz) OSC1 clock supplied from the pins OSC1 and OSC2 Clock from the ceramic resonator or the LC oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the raster color register (address 00D916), bits 3 to 6 of the clock source control register (addresses 00D016). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P2.
* * *
Table 9. Setting for P26/OSC1/XCIN, P27/OSC2/XCOUT OSD clock Sub-clock Function I/O Pin I/O Pin Register b7 of raster color register OSD control register b6 b5 1 0 0 0 0 0
I/O Port 1 1 0
Data slicer circuit
Data slicer clock (Note)
"0"
CC mode block
"1" "0"
OC3
OSD mode block
Ceramic * LC "10"
OSC1 clock
"1"
OC4
OC6, OC5
Oscillating mode for OSD
Note : To use data slicer clock, set bit 0 of data slicer control register to "1."
Fig. 64. Block Diagram of OSD Selection Circuit
61
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 66) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure 58) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 6 of the I/O polarity control register at address 00D816). A dot line is specified by bit 5 of the I/O polarity control register (refer to Figure 66). However, the field determination flag read out from the CPU is fixed to "0" at even field or "1" at odd field, regardless of bit 5.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 I/O polarity control register (PC) [Address 00D8 16]
B 0 1 2 3 4 5
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) OUT1 output polarity switch bit (PC3) OUT2 output polarity switch bit (PC4) Display dot line selection bit (PC5) (See note)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW
6 7
Field determination flag (PC6) Fix this bit to "0."
0 : Even field 1 : Odd field
1 0
R-- RW
Note: Refer to the corresponding figure (P63).
Fig. 65. I/O Polarity Control Register
62
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Both HSYNC signal and VSYNC signal are negative-polarity input Field Display dot line determination selection bit flag(Note)
HSYNC
Field
Display dot line
VSYNC and VSYNC control signal in microcomputer Upper : VSYNC signal Lower : VSYNC control signal in microcomputer
(n - 1) field (Odd-numbered) T1
0.25 to 0.50[ s] at f(XIN) = 8 MHz
Odd
0 (n) field (Even-numbered) T2 Even 0 (T2 > T1) 1
Dot line 1 Dot line 0
0 (n + 1) field (Odd-numbered) T3 Odd 1 (T3 < T2) 1
Dot line 0
Dot line 1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020816) to "0." 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CC mode 2345 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSD mode When the display dot line selection bit is "0," the " " font is displayed at even field, the " " font is displayed at odd field. Bit 6 of the I/O polarity control register can be read as the field determination flag : "1" is read at odd field, "0" is read at even field. 12 345 6 7 8 9 10 11 12 13 14 15 16
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in the microcomputer.
Fig. 66. Relation between Field Determination Flag and Display Font
63
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) Memory for OSD
There are 2 types of memory for OSD : ROM for OSD (addresses 1140016 to 13BFF16) used to store character dot data (masked) and RAM for OSD (addresses 080016 to 087F16) used to specify the characters and colors to be displayed. The following describes each type of memory. ROM for OSD (addresses 1140016 to 13BFF16) The ROM for OSD contains dot pattern data for characters to be displayed. To actually display the character code stored in this ROM, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the ROM for OSD) into the RAM for OSD. Data of the character font is specified shown in Figure 67.
OSD ROM address of character font data
OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit
Line number/character code/font bit
1
0
0
Line number
Character code
= "0A16" to "1D16" Line number Character code = "0016" to "FF16" ("7F16" and "8016" cannot be used) Font bit = 0 : left font 1 : right font
Line number
0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D
b7
Left font
b0 b7
Right font
b0
Data in OSD ROM
000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016
Character font
Fig. 67. OSD Character Data Storing Form
64
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : The 80-byte addresses corresponding to the character code "7F16" and "8016" in OSD ROM are the test data storing area. Set "FF16" to the area. (We stores the test data to this area and the different data from "FF16" is stored for the actual products.) The test data storing area : addresses 1100016 + (4 + 2n) ! 10016 + FE16 to 1100016 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) addresses 114FE16 to 1150116 addresses 116FE16 to 1170116 addresses 138FE16 to 1390116 addresses 13AFE16 to 13B0116 2 : The character code "0916" is used for "transparent space" when displaying Closed Caption. Therefore, set "0016" to the 40-byte addresses corresponding to the character code "0916." The transparent space font data storing area : addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 1100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19) addresses 1141216 and 1141316 addresses 1161216 and 1161316 addresses 1381216 and 1381316 addresses 13A1216 and 13A1316 Table 10. Contents of OSD RAM Block Display Position (from left) 1st character 2nd character 3rd character : 30th character 31st character 32nd character 1st character 2nd character 3rd character : 30th character 31st character 32nd character ... ...
RAM for OSD (addresses 080016 to 087F16) The RAM for OSD is allocated at addresses 080016 to 087F16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 13 shows the contents of the RAM for OSD. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write the color code 1 at 082016. The structure of the RAM for OSD is shown in Figure 68.
Block 1
Block 2
Character Code Specification 080016 080116 080216 : 081D16 081E16 081F16 084016 084116 084216 : 085D16 085E16 085F16
Color Code Specification 082016 082116 082216 : 083D16 083E16 083F16 086016 086116 086216 : 087D16 087E16 087F16
65
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Blocks 1, 2 b7 b0 b7 b0
RA6 RA5 RA4 RA3 RA2 RA1 RA0 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 (Note 1)
Color code 1
Character code (Note 3)
CC mode Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 Control of character color R Control of character color G Control of character color B OUT1/OUT2 control Flash control Underline control Italic control (Note 2) 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON Notes 1: Read value of bits 7 of the color code is "0." 2: For OUT1/OUT2 control, refer to "(8) OUT1/OUT2 signal." 3: "7F16" and "8016" cannot be used as character code. Fig. 68. OSD RAM 0: Color signal output OFF 1: Color signal output ON Control of character color R Control of character color G Control of character color B Character code Specification of character code in OSD ROM Character code Bit name Function Bit name
OSD mode Function
Specification of character code in OSD ROM
0: Color signal output OFF 1: Color signal output ON
OUT1/OUT2 control Control of background color R Control of background color G Control of background color B
(Note 2) 0: Color signal output OFF 1: Color signal output ON
(6) Character color
The color for each character is displayed by the color code. The kinds and specification method of character color are different depending on each mode. CC mode ...............7 kinds OSD mode Specified by bits 0 (R), 1 (G), and 2 (B) of the color code
(7) Character background color
The character background color can be displayed in the character display area only in the OSD mode. The character background color for each character is specified by the color code. The kinds and specification method of character background color are different depending on each mode. OSD mode ............... 7 kinds Specified by bits 4 (R), 5 (G), and 6 (B) of the color code
* *
*
Note : The character background color is displayed in the following part : (character display area)-(character font)-(border). Accordingly, the character background color does not mix with these color signal.
66
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(8) OUT1, OUT2 signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by display mode, bit 3 (RA3) of color code (refer to Figure 65), bit 5 of the block control register i (refer to Figure 54). The set-
ting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 69. Note : When OUT2 signal is output, set bit 7 of OSD port control register to "1."
A
A'
Block Control Register i Display Mode OUT1/OUT2 Output
Control Bit (b5)
OUT1/OUT2 Control b3 (=RA3) of Color Code 0
Output Waveform (A-A')
OUT1 = FONT/BORDER OUT2 = "L" OUT1 = AREA OUT2 = "L"
0 (OUT1 output is controlled by RA3)
1 OSD 1 (OUT2 output is controlled by RA3) 0
OUT1 = FONT/BORDER OUT2 = "L" OUT1 = FONT/BORDER OUT2 = AREA OUT1 = FONT
1
0 (OUT1 output is controlled by RA3) CC 1 (OUT2 output is controlled by RA3)
0
OUT2 = "L" OUT1 = AREA OUT2 = "L" OUT1 = FONT OUT2 = "L" OUT1 = FONT
1
0
1
OUT2 = AREA
Notes 1 : FONT/BORDER.....In the OSD mode (Border ON), OUT1 outputs to the area of font and border. In the OSD mode (Border OFF), OUT1 outputs to only the font area. AREA.....................OUT1/OUT2 outputs to entire display area of character. FONT.....................In the CC mode, OUT1 outputs to font area. 2 : When the automatic solid space function is OFF in the CC mode, AREA outputs according to bit 3 of color code. When it is ON, the solid space is automatically output by a character code regardless of RA3.
Fig. 69. Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
67
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(9) Attribute
The attributes (border, flash, underline, italic) are controlled to the character font. The attributes for each character are specified by the color code (refer to Figure 68). The attributes to be controlled are different depending on each mode. CC mode ..................... Flash, underline, italic OSD mode .................. Border
Under line
The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by bit 5 of the color code. The color of underline is the same color as that of the character font.
Flash
The parts of the character font, the underline, and the character background are flashed only in the CC mode. The color signals (R, G, B, OUT1) of the character font and the underline are controlled by bit 5 of the color code. The character font part (solid box) is not flashed. The flash cycle bases on the VSYNC count. * VSYNC cycle ! 48 800 ms (at display ON) * VSYNC cycle ! 16 267 ms (at display OFF)
Italic
The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic is controlled by bit 6 of the color code. The display example of the italic and underline is shown in Figure 70. In this case, "R" is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 71).
68
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Color code
Color code
Bit 5
Bit 6
Bit 5
Bit 6
0
0
1
0
(a) Ordinary
(b) Underline
Color code
Bit 5
Bit 6
0
1
(c) Italic
Fig. 70. Example of Attribute Display (in CC Mode)
Italic on one side
Italic on both sides
Bit 6 of color code
1
0
0
1
1
0
1
Note : The wavy-lined is the boundary of character color
Fig. 71. Example of Italic Display
69
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Border The border is output around of character font (all bordered) in the OSD mode. The border ON/OFF is controlled by bit 0 and 1 of the block control register i (refer to Figure 56). The OUT1 signal is used for border output. The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font.
Notes 1 : The border dot area is the shaded area as shown in Figure 72. 2 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 74 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 74 B).
OSD mode
16 dots
Character font area
All bordered
1 dot width of border 1 dot width of border
Fig. 72. Example of Border Display
y x Vertical dot size of character font
20 dots
Border dot size
1/2H
1H, 2H, 3H
Horizontal size (x) Vertical size (y)
1Tc (OSD clock cycle divided in pre-divide circuit) 1/2H 1H
Fig. 73. Horizontal and Vertical Size of Border
70
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Character boundary B
Character boundary A
Character boundary B
Fig. 74. Border Priority
71
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Multiline Display
The M37273MF-XXXSP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block.
Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D216, 00D316), an OSD interrupt request does not occur (refer to Figure 75 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 75 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 75 (C)).
Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display)
"OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request"
On display (OSD interrupt request occurs at the end of block display) (A)
Off display (OSD interrupt request does not occur at the end of block display)
Block 1 "OSD interrupt request" Block 1 Block 2
No "OSD interrupt request" "OSD interrupt request"
Block 2 "OSD interrupt request" Block 1' "OSD interrupt request"
Window In CC mode (B)
(C)
Fig. 75. Note on Occurence of OSD Interrupt
72
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(11) Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : * the character area except character code "0916 " * the character area on the left and right sides of character code "0916 " This function is turned on and off by bit 1 of the OSD control register (refer to Figure 55).
When setting the character code "05 16" as the character A, "06 16" as the character B.
(OSD RAM) Character to be displayed
05 09 09 09 06 06
16 16 16 16 16 16
***
06 09 09 06
16 16 16 16
(Display screen)
***
1st character
2nd character
No blank output
31st character
32nd character
The solid space is automatically output on the left side of the 1st character and on the right side of the 32nd character by setting the 1st and 32nd of the character code.
Fig. 76. Display Screen Example of Automatic Solid Space Note : The character code "0916" is used for "transparent space" when displaying Closed Caption. Therefore, set "0016" to the 40-byte addresses corresponding to the character code "0916." The transparent space font data storing area : addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 1100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19) addresses 1141216 and 1141316 addresses 1161216 and 1161316 addresses 1381216 and 1381316 addresses 13A1216 and 13A1316 ...
73
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(12) Window Function
This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by the window registers 1 and bit 7 of block control register 1. The bottom boundary is set by window registers 1 and bit 7 of block control register 2. This function is turned on and off by bit 2 of the OSD control register (refer to Figure 55). The structure of window registers 1 and 2 is shown in Figure 78 and 79. Notes 1: Do not set values except "0016" to the window register 1 when bit 7 of block control register 1 is "0." 2: Set the register value fit for the following condition : (Value of top boundary of window) < (Value of bottom boundary of window)
ABCDE F GH I J
OSD mode
Top boundary of window
CC mode CC mode CC mode Window
KL
MNO
PQRST UV WX Y
Screen
OSD mode
Bottom boundary of window
Fig. 77. Example of Window Function
74
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window register 1 (WN1) [Addresses 00D616] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WN10 to WN17) (See note 1)
Top boundary position (low-order 8 bits) Indeterminate R W TH ! (setting value of BC17 ! 162 + setting value of low-order 4 bits of WN1 ! 161 + setting value of low-order 4 bits of WN1 ! 160)
Notes 1: Set values except "00 16" to the WN1 when BC17 is "0." 2: TH is cycle of HSYNC. 3: BC17 is bit 7 of the clock control register 1.
Fig. 78. Window Register 1
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window register 2 (WN2) [Addresses 00D716] B Name Functions After reset RW
0 Control bits of window to bottom boundary 7 (WN20 to WN27) (See note 1)
Bottom boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of BC17 ! 162 + setting value of low-order 4 bits of WN2 ! 161 + setting value of low-order 4 bits of WN2 ! 160)
Notes 1: Set values fit for the following condition: WN1Fig. 79. Window Register 2
75
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(13) OSD Output Pin Control
The OSD output pins R, G, B, OUT1, and OUT2 can also function as ports P52, P53, P54, P55, and P10. When using OUT2 pin, set bit 0 of the port P1 direction register (address 00C316) to "1" (output mode). After that, switch between the OSD output function and the port function by the OSD port control register. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the I/O polarity control register (address 00D8) . Set a bit to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 65). The structure of the OSD port control register is shown in Figure 80.
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (PF) [Address 00CB 16]
B
Name
Functions
After reset R W 0 RW RW RW RW RW R-- RW
0, 1 Fix these bits to "0." 2 3 4 5 6 7 Port P52 output signal selection bit (PF2) Port P53 output signal selection bit (PF3) Port P54 output signal selection bit (PF4) Port P55 output signal selection bit (PF5) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P53 output
0
0 0 0 0 0
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Port P10 output signal selection bit (PF7) 0 : Port P10 output 1 : OUT2 signal output
Fig. 80. OSD Port Control Register
76
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(14) Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 4 to 0 of the raster color register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 7 raster colors can be obtained. If the OUT1 pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, and B pins have been set to output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 81, a character "1") and the character background output during 1 horizontal scanning period. This ensures that character color/ character background color is not mixed with the raster color. The structure of the raster color register is shown in Figure 82, the example of raster coloring is shown in Figure 81.
: Character color "RED" (R) : Border : Background color "MAGENTA" (R and B) : Raster color "BLUE" (B and OUT1)
A
A'
HSYNC OUT1 R G B
Fig. 81. Example of Raster Coloring
Signals across A-A'
77
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 00D916] B 0 1 2 3 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Raster color OUT1 control bit (RC3) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset R W 0 0 0 0 0 RW RW RW RW RW
4 Raster color OUT2 control bit (RC4) 5, 6 Fix these bits to "0." 7 Port function selection bit (RC7)
0 0 : OSC1/XCIN, OSC2/XCOUT 1 : P26, P27 0
RW RW
Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register.
Fig. 82. Raster Color Register
78
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes ! 2 blocks. Block 1 : addresses 030016 to 031F16 Block 2 : addresses 032016 to 033F16 Set an address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. When the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. The ROM correction function is controlled by the ROM correction enable register. Notes 1 : Specify the first address (op code address) of each instruction as the ROM correction address. 2 : Use the JMP instruction (total of 3 bytes) to return from the main program to the correction program. 3 : Do not set the same ROM correction address to blocks 1 and 2.
ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order)
020A16 020B16 020C16 020D16
Fig. 83. ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E16] B
0 1 2 to 7
Name
Block 1 enable bit (RC0) Block 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0 0
RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 84. ROM Correction Enable Register
79
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V 10 %, hold the ______ RESET pin at LOW for 2 s or more, then return it to HIGH. Then, as shown in Figure 86, reset is released and the program starts from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 5 to 8. An example of the reset circuit is shown in Figure 85. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V.
Poweron 4.5 V Power source voltage 0 V
Reset input voltage 0 V
0.9 V
27 1 5
M51953AL
Vcc
30
RESET
4 3 0.1 F 26
Vss
M37273MF-XXXSP
Fig. 85. Example of Reset Circuit
XIN
RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) ? ? ? ?
01, S
01, S-1 01, S-2
FFFE
FFFF
ADH, ADL
Reset address from the vector table ? ? ? ADL ADH
Notes 1 : f(XIN) and f( ) are in the relation : f(XIN) = 2*f ( ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF 16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.
Fig. 86. Reset Sequence
80
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
CLOCK GENERATING CIRCUIT
The M37273MF-XXXSP has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock, clear bits 5 and 6 of the OSD control register to "0." To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to "1."
(3) Low-Speed Mode
If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to "1." When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption. To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to "0." At reset, this bit is set to "1" and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to "1" by software before executing.
Oscillation Control (1) Stop mode
The built-in clock generating circuit is shown in Figure 78. When the STP instruction is executed, the internal clock stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and "FF16" is set in timer 3 and "0716" is set in timer 4. Select f(XIN)/16 or f(XCIN)/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to "0" before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock keeps its "H" level until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used.
M37273MF-XXXSP XCIN
Rf
XCOUT
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 87. Ceramic Resonator Circuit Example
(2) Wait mode
When the WIT instruction is executed, the internal clock stops in the "H" level but oscillation continues. This wait state is released at reset or when an interrupt is accepted (Note). Since oscillation does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) OSD interrupt (3) Timers 1 and 2 interrupts using TIM2 pin input as count source (4) Timer 3 interrupt using TIM3 pin input as count source (5) Data slicer interrupt (6) Multi-master I2C-BUS interface interrupt (7) f(XIN)/4096 interrupt (8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source (9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source (10) A-D conversion interrupt
XCIN
M37273MF-XXXSP XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss
Fig. 88. External Clock Input Circuit Example
81
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
XCIN
XCOUT
OC5 OC6 (Notes 1, 4) XIN XOUT "1" 1/2 "0" Internal system clock selection bit (Notes 1, 3) 1/8 "1" "0" Timer 3 count source selection bit (Notes 1, 2) Timing (Internal clock) Timer 3 count stop bit (Notes 1, 2) Timer 3 Timer 4 count stop bit (Notes 1, 2) Timer 4
Main clock (XIN-XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S S Q Q S
Reset STP instruction
R
STP instruction
WIT instruction
R
R
Reset Interrupt disable flag I Interrupt request
Notes 1 : The value at reset is "0." 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register. 4 : Refer to the structure of OSD control register.
Fig. 89. Clock Generating Circuit Block Diagram
82
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Reset
High-speed operation start mode
WIT instruction 8MHz oscillating 32kHz oscillating is stopped ("H") Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8MHz oscillating 32kHz oscillating f( ) = 4MHz
STP instruction 8MHz stopped 32kHz stopped is stopped ("H") Interrupt (Note 1) External INT CM7 = 0
CM7 = 1
WIT instruction 8MHz oscillating 32kHz oscillating is stopped ("H") Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f( ) = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped is stopped ("H") Interrupt (Note 2)
CM6 = 0 The program must allow time for 8MHz oscillation to stabilize
CM6 = 1
8MHz stopped 32kHz oscillating is stopped ("H") Timer operating (Note 3)
WIT instruction 8MHz stopped 32kHz oscillating f( ) = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped = stopped ("H") Interrupt (Note 2)
CPU mode register (Address : 00FB16) CM6 : Main clock (X IN-XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X CIN pin. The
indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock divided by 8 is used as the timer count source, the frequency of the count source is 2kHz.
Fig. 90. State Transitions of System Clock
83
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 6 of the OSD control register (address 00D016).
ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User's Manual for details.
MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 User's Manual for details.
PROGRAMMING NOTES
(1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1 mF) directly between the VCC pin-VSS pin, AVCC pin-VSS pin, and the VCC pin-CNVSS pin, using a thick wire.
OSC1
OSC2
L C1 C2
Fig. 91. Display Oscillation Circuit
AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will oper______ ate by connecting the following circuit to the RESET pin.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
Circuit example 1
(1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies)
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage.
Fig. 92. Auto-clear Circuit Example
84
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PROM Programming Method
The built-in PROM of the One Time PROM version (blank) and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter.
Product M37273EFSP
Name of Programming Adapter PCA7426G02
The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 93 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution : The screening temparature is far higher than the storage temparature. Never expose to 150 C exceeding 100 hours.
Fig. 93. Programming and testing of One Time PROM version
85
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC, AVCC VI VI Input voltage Input voltage Parameter Power source voltage VCC, AVCC CNVSS P00-P07, P10-P17, P20-P27, ______ P30, P31, XIN, P50, P51, RESET, CVIN P06, P07, P10-P17, P20-P27, P30, P31, P52-P57, P60-P67, XOUT P00-P05 P10-P17, P20-P27, P30, P31, P52-P57, P60-P67 P06, P07, P10, P15-P17, P20-P23, P26, P27, P52-P57, P60-P67 P11-P14 P00-P05 P24, P25, P30, P31 Ta = 25 C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V
VO VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg
Output voltage Output voltage Circuit current Circuit current Circuit current Circuit current Circuit current Power dissipation
-0.3 to VCC + 0.3 -0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 -10 to 70 -40 to 125
V V mA mA mA mA mA mW C C
Operating temperature Storage temperature
RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted)
Symbol VCC, AVCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 fhs4 VI Parameter Power source voltage (Note 4), During CPU, OSD, data slicer operation Power source voltage HIGH input voltage HIGH input voltage LOW input voltage LOW input voltage LOW input voltage (Note 6) P00-P07, P10-P17, P20-P27, P30, P31, ______ P50, P51, HSYNC, VSYNC, RESET, XIN SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) P00-P07, P10-P17, P20-P27, P30, P31 SCL1, SCL2, SDA1, SDA2, (When using I2C-BUS)
______
Limits Min. 4.5 0 0.8VCC 0.7VCC 0 0 0 Typ. 5.0 0 Max. 5.5 0 VCC VCC 0.4 VCC 0.3 VCC 0.2 VCC
Unit V V V V V V V
P50, P51, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK
HIGH average output current (Note 1) P10-P17, P20-P27, P30, P31, P52-P57, P60-P67 LOW average output current (Note 2) P06, P07, P10, P15-P17, P20-P23, P26, P27, P52-P57, P60-P67 LOW average output current (Note 2) P11-P14 LOW average output current (Note 2) P00-P05 LOW average output current (Note 3) P24, P25, P30, P31 Oscillation frequency (for CPU operation) (Note 5) Oscillation frequency (for sub-clock operation) Oscillation frequency (for OSD) Input frequency Input frequency Input frequency Input frequency Input amplitude video signal OSC1 TIM2, TIM3, INT1, INT2, INT3 SCLK SCL1, SCL2 Horizontal sync. signal of video signal CVIN 15.262 1.5 15.734 2.0 XIN XCIN 7.9 29 26.5 8.0 32 27.0
1 2 6 1 10 8.1 35 27.0 100 1 400 16.206 2.5
mA mA mA mA mA MHz kHz MHz kHz MHz kHz kHz V
86
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted)
Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, OSD OFF f(XIN) = 8 MHz Data slicer OFF OSD ON Data slicer ON VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Wait mode VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = "0," CM6 = "1") Stop mode VOH HIGH output voltage P10-P17, P20-P27, P30, P31, P52-P57, P60-P67 P00-P07, P10, P15- P17, P20-P23, P26, P27, P52-P57, P60-P67 P24, P25, P30, P31 P11-P14 P50, P51, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, ______ SCL2, SDA1, SDA2, RESET VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V IOL = 3 mA IOL = 6 mA VT+-VT- Hysteresis (Note 6) 0.5 2.4 V Limits Min. Typ. 15 30 60 Max. 30 mA 45 200 Unit
A
2 25
4 100
mA
A
1 10
VOL
LOW output voltage
0.4 3.0 0.4 0.6 1.3 V 5 V
LOW output voltage LOW output voltage
IIZH
HIGH input leak current P06, P07, P10-P17, P50, P51, VCC = 5.5 V ______ P20-P27, P30, P31, RESET VI = 5.5 V HIGH input leak current P00-P05 LOW input leak current P00-P07, P10-P17, P20-P27, ______ P30, P31, P50, P51, RESET I2C-BUS*BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) VCC = 5.5 V VI = 12 V VCC = 5.5 V VI = 0 V VCC = 4.5 V
A
10 5
IIZL RBS Notes 1: 2: 3: 4:
A
130
The total current that flows out of the IC must be 20 mA or less. The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less. The total average input current for ports P30, P31, P24, P25 to IC must be 20 mA or less. Connect 0.1 F or more capacitor externally between the power source pins VCC-VSS and AVCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. 6: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20, P22 have the hysteresis when these pins are used as serial I/O pins. 7: Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports * When the same limits: I/O port name. * When the limits of functins except ports are different from I/O port limits: function pin name.
87
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D COMPARATOR CHARACTERISTICS
Symbol -- -- -- VOT VFST Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Parameter
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Test conditions Limits Min. 0 0 IOL (SUM) = 0mA 0 0 Typ. Max. 6 1 0.9 2 -2 Unit bits LSB LSB LSB LSB
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 250 4.7 4.0 0 4.0 300 Standard Clock Mode Parameter Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit ms ms ms ns ms ms ns ns ms ms
Note: Cb = total capacitance of 1 bus line
SDA tHD:STA tSU:STO
tBUF tLOW P SCL S
tR
tF Sr P
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
S : Start condition Sr : Restart condition P : Stop condition
Fig. 94. Definition Diagram of Timing on Multi-master I2C-BUS
88
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PACKAGE OUTLINE
89
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH11-94B < 76A0 > Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37273MF-XXXSP MITSUBISHI ELECTRIC
Date :
Receipt
Section head signature Supervisor signature
Note : Please fill in all items marked * .
signature Issuance
Company name * Customer Date issued Date :
TEL ( )
Submitted by
Supervisor
* 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used) (hexadecimal notation)
27C101
EPROM address 000016 Product name 000F16 100016 FFFF16 1140016
OSD ROM ASCII code : `M37273MF -'
data ROM (60K )
13BFF16 1FFFF16
(1)
(2)
Set "FF16" in the shaded area and in the test data storing area for OSD ROM (refer to page 3/3). Moreover, set "0016" in the "transparent space" font data storing area. If writing data by mistake, a hindrance for ship may occur. Therefore, extreme care must be taken to verify that the specified data is stored in the corresponding area in the submitted EPROMs. Write the ASCII codes that indicate the product name of "M37273MF-" to addresses 0000 16 to 000F16.
EPROM data check item (Confirm the EPROM data and check " " the appropriate box) q Is "FF16" set in the shaded area and in the test data storing area for OSD ROM Yes (refer to page 3/3)? Yes q Is "0016" set in the "transparent space" font data storing area (refer to page 3/3)? q Are the ASCII codes that indicates the product name of "M37273MF-" to Yes addresses 000016 to 000F16 ? * 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (52P4B for M37273MF-XXXSP) and attach to the mask ROM confirmation form.
(1/3)
90
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH11-94B < 76A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37273MF-XXXSP MITSUBISHI ELECTRIC
How to Write the Product Name and Character ROM Data onto EPROMs
Addresses 000016 to 000F16 store the product name, and addresses 11400 16 to 13BFF16 store the character pattern. Both address and data are described in hexadecimal notation. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 1. How to input the name of the product with the ASCII code: ASCII codes `M37273MF-' are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
`M' = `3' = `7' = `2' = `7' = `3' = `M' = `F' =
4D 33 37 32 37 33 4D 46
16 16 16 16 16 16 16 16
`-' = 2 D FF FF FF FF FF FF FF
16 16 16 16 16 16 16 16
2. Inputting the character ROM Input the character ROM data to character ROM. For the character ROM data, see the next page and on.
91
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
GZZ-SH11-94B < 76A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37273MF-XXXSP MITSUBISHI ELECTRIC
Font data must be stored in the proper OSD ROM address according to the following table. (1)OSD ROM address of character font data
OSD ROM address bit Line number / Character code / Font bit
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
0
0
Line number
Character code
Font bit
Line number = 0A 16 to 1D16 Character code = 00 16 to FF16 (Do not set 7F16 to 8016.) Font bit = 0 : Left font 1 : Right font Example ) The font data "60" (shaded area ) of the character code "AA
2 16"
is stored in address
10010010101010100
=1255416.
Left font Line number 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16
Right font
Line number
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(1) Character code "AA 16" Notes 1 : The 80-byte addresses corresponding to the character code "7F16" and "8016" in OSD ROM are the test data storning area. Set "FF 16" to the area (We stores the test data to this area and the different data from "FF 16" is stored for the actual products.) The test data storing area : addresses 1100016 + (4 + 2n) ! 10016 + FE16 to 11000 16 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) addresses 114FE 16 to 1150116 addresses 116FE 16 to 1170116
* * *
2 : The character code "09 16" is used for "transparent space" when displaying Closed Caption. Therefore, set "0016" to the 40-byte addresses corresponding to the character code "09 16." The transparent space font data storing area : addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 11000 16 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19)
addresses 11412 16 and 1141316 addresses 11612 16 and 1161316
* * *
addresses 138FE 16 to 1390116 addresses 13AFE 16 to 13B0116 (3/3)
addresses 13812 16 and 1381316 addresses 13A12 16 and 13A1316
92
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
52P4B (52-PIN SHRINK DIP) MARK SPECIFICATION FORM
93
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Pin Configuration (top view)
P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P56 P02/PWM2 P57 P03/PWM3 P60 P04/PWM4 P05/PWM5 P06/INT2/AD4 P61 P07/INT1 P62 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS
1 2 3 4 5 6
52 51 50 49 48 47
P52/R P53/G P54/B P55/OUT1 P63 P20/SCLK P64 P21/SOUT P65 P22/SIN P66 P10/OUT2 P67 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC
M37273MF-XXXSP, M37273EFSP
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Outline 52P4B
94
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Memory Map
000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 033F16 06FF16 Not used RAM for OSD (Note) (128 bytes) 080016 087F16 100016 ROM for OSD (10K bytes) Not used Zero page SFR1 area
1000016
RAM (1472 bytes)
SFR2 area Not used ROM correction memory (RAM) Block 1: addresses 0300 16 to 031F16 Block 2: addresses 0320 16 to 033F16 Not used
1140016 13BFF16
ROM (60K bytes)
Not used
FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16
Note : Refer to table 10. contents of RAM for OSD.
95
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Memory Map of Special Function Register (SFR)
s SFR1 Area (addresses C016 to DF16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Register
b7
Bit allocation
b0 b7
State immediately after reset ? 0016 ? 0016 ? 0016 00 0016 ? ? ? 0016 0016 ? ? ? 0016 0016 ? ? ? ? ? ? 4016 0016 ? ? 0016 0016 0016 0016
b0
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3)
T3SC P31 P30 P31C P30C P31D P30D
0
0
0
0
?
?
Port P5 (P5) OSD port control register (PF) Port P6 (P6) Caption data register 3 (CD3) Caption data register 4 (CD4) OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Vertical position register 1 (VP1) Vertical position register 2 (VP2) Window register 1 (WN1) Window register 2 (WN2) I/O polarity control register (PC) Raster color register (RC) PF7
PF5 PF4 PF3 PF2
0
0
CDL27 CDL26 CDL25 CDL24 CDL23 CDL22 CDL21 CDL20 CDH27 CDH26 CDH25 CDH24 CDH23 CDH22 CDH21 CDH20
0
OC6 OC5 OC4 OC3 OC2 OC1 OC0 HP6 HP5 HP4 HP3 HP2 HP1 HP0
BC17 BC16 BC15 BC14 BC13 BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23 BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 WN17 WN16 WN15 WN14 WN13 WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23 WN22 WN21 WN20
0
RC7
PC6 PC5 PC4 PC3 PC2 PC1 PC0
0
0
RC4 RC3 RC2 RC1 RC0
Interrupt input polarity control register (RE)
INT3 INT2 INT1
0016 0016 0016
96
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR1 Area (addresses E016 to FF16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address
Register
b7
Bit allocation 1 0 1 0 0 1
b0 b7
DSC20
State immediately after reset 0 ? 0016 0? 0016 0016 0016 01 00 0016 0016 0016 ? 0016 ?0 0016 0716 FF16 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 11 0016 0016 0016 0016 ? 0
b0
E016 Data slicer control register 1 (DSC1) 0 E116 Data slicer control register 2 (DSC2) E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16
Caption data register 1 (CD1) Caption data register 2 (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register 2 Data slicer test register 1 Synchronous signal counter register (HC) Serial I/O register (SIO) Serial I/O mode register (SM) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 5 (T5) Timer 6 (T6) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2 C address register (S0D) I2C status register (S1)
DSC12 DSC11 DSC10
DSC25 DSC24 DSC23
?
?
CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17 CDH16 CDH15 CDH14 CDH13 CDH12 CDH11 CDH10 CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3
0
1
0
CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0
0 0
0 0
0 ?
0 0
0 0
1 0
HC5 HC4 HC3 HC2 HC1 HC0
0
SM6 SM5
0
ADC14
SM3 SM2 SM1 SM0
ADC12 ADC11 ADC10
0
0
0
0
0
0
ADC25 ADC24 ADC23 ADC22 ADC21 ADC20
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB
BSEL1 BSEL0
PIN
AL AAS AD0 LRB
0
0
0
0
0
?
I2C control register (S1D) I2C clock control register (S2) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
10BIT ALS ESO BC2 BC1 BC0 SAD ACK FAST ACK CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
CM7 CM6 CM5
1
1
CM2
0
0
0
0
1
1
0
0
IN3R VSCR OSDR TM4R TM3R TM2R TM1R
0
TM56R IICR IN2R CKR SIR DSR IN1R CK0
IN3E VSCE OSDE TM4E TM3E TM2E TM1E
TM56C TM56E IICE IN2E CKE SIE DSE IN1E
97
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR2 Area (addresses 20016 to 20F16)
0 : "0" immediately after reset Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
:
Name
:
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Address
Register
b7
Bit allocation
b0 b7
State immediately after reset ? ? ? ? ? ? ? ?
b0
20016 PWM0 register (PWM0) 20116 PWM1 register (PWM1) 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16
PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5)
0016 0016
PWM mode register 1 (PM1) PWM mode register 2 (PM2) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)
PM13 PM10
?
?
?
0
0
PM25 PM24 PM23 PM22 PM21 PM20
ADH17 ADH16 ADH15 ADH14 ADH13 ADH12 ADH11 ADH10 ADL17 ADL16 ADL15 ADL14 ADL13 ADL12 ADL11 ADL10 ADH27 ADH26 ADH25 ADH24 ADH23 ADH22 ADH21 ADH20 ADL27 ADL26 ADL25 ADL24 ADL23 ADL22 ADL21 ADL20
RC1 RC0
?0 0016 ? ? ? ? 0016 ?
?
?
0
98
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Internal State of Processor Status Register and Program Counter at Reset

0 : "0" immediately after reset
:
Name
:
Function bit 1 : "1" immediately after reset ? : Undefined immediately after reset
: No function bit 0 : Fix this bit to "0" (do not write "1") 1 : Fix this bit to "1" (do not write "0")
Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation
b0 b7
State immediately after reset
b0
N
V
T
B
D
I
Z
C
?
????1?? Contents of address FFFF16 Contents of address FFFE16
99
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
Example
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00
Bit attributes (Note 2) Bits Values immediately after reset release (Note 1)
CPU mode register (CPUM) (CM) [Address FB 16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 0 1 1 0 RW RW RW RW
2
Stack page selection bit (Note) (CM2)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "0." b7 b6 6, 7 Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0******"0" after reset release 1******"1" after reset release ?******Indeterminate after reset release 5
2: Bit attributes******The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : W******Write R******Read ******Write enabled ******Read enabled ! ******Read disabled ! ******Write disabled V ******"0" can be set by software, but "1" cannot be set.
100
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i=0 to [Addresses 00C116, 00C316, 00C516] 2) B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Port Pi Direction Register
Address 00C116, 00C316, 00C516
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C7 16]
B 0 1 2 3
Name Port P3 direction register
Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode
After reset R W 0 0 0 0 0 0 RW RW RW RW R-- RW
Port P30 output structure selection bit (P30C) Port P31 output structure selection bit (P30C)
0 : CMOS output 1 : N-channel open-drain output 0 : CMOS output 1 : N-channel open-drain output
4, 5, Nothing is assigned. These bits are write disable bits. 7 When these bits are read out, the values are "0." 6 Timer 3 count source selection bit (T3SC) Refer to Timer section.
Port P3 Direction Register
Address 00C716
101
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (PF) [Address 00CB16]
B
Name
Functions
After reset R W 0 RW RW RW RW RW R-- RW
0, 1 Fix these bits to "0." 2 3 4 5 6 7 Port P52 output signal selection bit (PF2) Port P53 output signal selection bit (PF3) Port P54 output signal selection bit (PF4) Port P55 output signal selection bit (PF5) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P53 output
0 0 0 0 0 0
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Port P10 output signal selection bit (PF7) 0 : Port P10 output 1 : OUT2 signal output
OSD Port Control Register
Address 00CB16
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 OSD control register (OC) [Address 00D0 16] B 0 1 2 3 Name OSD control bit (OC0) (See note) Automatic solid space control bit (OC1) Window control bit (OC2) CC mode clock selection bit (OC3) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : OFF 1 : ON 0 : OFF 1 : ON 0 : Data slicer clock 1 : Clock from OSC1 pin 0 : Data slicer clock 1 : Clock from OSC1 pin
b6 b5
After reset R W 0 0 0 0 0 RW RW RW RW RW
4 OSD mode clock selection bit (OC4) 5, 6 OSC1 clock selection bit (OC5, OC6)
0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set.
0
RW
7 Fix this bit to "0."
0
RW
Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC.
OSD Control Register
Address 00D016
102
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00D116] Functions 0 Control bits of horizontal Horizontal display start positions 128 steps (0016 to 7F16) to display start positions 6 (HP0 to HP6) (1 step is 4TOSC) 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Note: The setting value synchronizes with the V SYNC. B Name After reset R W 0 RW
0
R--
Horizontal Position Register
Address 00D116
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D216 and 00D316] B Name
b1 b0
Functions 0 0 1 1
b4
After reset
RW
0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) 2, 3 Dot size selection bits (BCi2, BCi3) (See note 2 and 3) 4 Pre-divide ratio selection bit (BCi4) (See note 2 and 3) 5
Indeterminate R W
0: Display OFF 1: CC mode 0: OSD mode (Border OFF) 1: OSD mode (Border ON)
b3 0 0 1 1 0 0 1 1 b2 0 1 0 1 0 1 0 1 Pre-divide Ratio Dot Size 1Tc 1Tc 2Tc 3Tc 1Tc 1Tc 2Tc 3Tc ! 1/2H ! 1H ! 2H ! 3H ! 1/2H ! 1H ! 2H ! 3H
Indeterminate R W
0
!2
Indeterminate R W
1
!3
OUT1/OUT2 output 0: OUT1 output control 1: OUT2 output control control bit (BCi5) (See note 1) Vertical display start position control bit (BCi6) Window top/bottom boundary control bit (BCi7) BC16: Block 1 BC26: Block 1 BC17: Window top boundary BC27: Window bottom boundary
Indeterminate R W
6
Indeterminate R W
7
Indeterminate R W
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is "0." Bit RA3 of OSD RAM controls OUT2 output when bit 5 is "1." 2: Tc : OSD clock cycle divided in the pre-divide circuit 3: H : H SYNC
Block Control Register
Address 00D216, 00D316
103
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Functions After reset RW
0 Control bits of vertical to display start positions 7 (VPi0 to VPi7) (See note)
Vertical display start positions Indeterminate R W (low-order 8 bits) TH ! (setting value of BCi6 ! 162 + setting value of low-order 4 bits of VPi ! 161 + setting value of low-order 4 bits of VPi ! 160)
Note: Set values except "00 16" to VPi when BCi6 is "0."
Vertical Position Register
Address 00D416, 00D516
Window Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window register 1 (WN1) [Addresses 00D616] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WN10 to WN17) (See note 1)
Top boundary position (low-order 8 bits) Indeterminate R W TH ! (setting value of BC17 ! 162 + setting value of low-order 4 bits of WN1 ! 161 + setting value of low-order 4 bits of WN1 ! 160)
Notes 1: Set values except "00 16" to the WN1 when BC17 is "0." 2: TH is cycle of HSYNC. 3: BC17 is bit 7 of the clock control register 1.
Window Register 1
Address 00D616
Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window register 2 (WN2) [Addresses 00D716] B Name Functions After reset RW
0 Control bits of window to bottom boundary 7 (WN20 to WN27) (See note 1)
Bottom boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of BC17 ! 162 + setting value of low-order 4 bits of WN2 ! 161 + setting value of low-order 4 bits of WN2 ! 160)
Notes 1: Set values fit for the following condition: WN1Window Register 2
Address 00D716
104
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 I/O polarity control register (PC) [Address 00D816]
B 0 1 2 3 4 5
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) OUT1 output polarity switch bit (PC3) OUT2 output polarity switch bit (PC4) Display dot line selection bit (PC5) (See note)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW
6 7
Field determination flag (PC6) Fix this bit to "0."
0 : Even field 1 : Odd field
1 0
R-- RW
Note: Refer to the corresponding figure (P63).
I/O Polarity Control Register
Address 00D816
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 00D916] B 0 1 2 3 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Raster color OUT1 control bit (RC3) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset R W 0 0 0 0 0 RW RW RW RW RW
4 Raster color OUT2 control bit (RC4) 5, 6 Fix these bits to "0." 7 Port function selection bit (RC7)
0 0 : OSC1/XCIN, OSC2/XCOUT 1 : P26, P27 0
RW RW
Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register.
Raster Color Register
Address 00D916
105
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC16]
B 0 1 2 3 to 7
Name INT1 polarity switch bit (INT1) INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3)
Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
After reset 0 0 0 0
RW RW RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Interrupt Input Polarity Register
Address 00DC16
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 01100 Data slicer control register 1(DSC1) [Address 00E016] B 0 Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 0 RW RW RW RW RW
Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3, 4, Fix these bits to "0." 7 5, 6 Fix these bits to "1."
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Data Slicer Control Register 1
Address 00E016
106
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 1 Data slicer control register 2 (DSC2) [Address 00E116]
B 0
Name Caption data latch completion flag 1 (DSC20)
Functions
After reset
RW
Indeterminate R -- 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) RW
1
Fix this bit to "1."
2, 7 Test bit 3 4 Field determination flag (DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24)
Indeterminate R -- Indeterminate R -- 0 RW
5 6
0: Match V-pulse shape determination flag (DSC25) 1: Mismatch Fix this bit to "o."
Indeterminate R -- 0 RW
Definition of fields 1 (F1) and 2 (F2) F1: Hsep Vsep F2: Hsep Vsep
Data Slicer Control Register 2
Address 00E116
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E416] B 0 to 2 3 to 7 Test bits Name Read-only Functions After reset R W 0 R--
Clock run-in detection bit (CRD3 to CRD7)
Number of reference clocks to be counted in one clock run-in pulse period.
0
R--
Clock Run-in Detection Register
Address 00E416
107
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 Data clock position register (DPS) [Address 00E516]
B 0 2 1 3 4 to 7
Name Fix these bits to "0." Fix this bit to "1." Data clock position set bits (DPS3 to DPS7)
Functions
After reset R W 1 0 0 1 0 RW RW RW
Data Clock Position Register
Address 00E516
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616]
B 0 to 4 5
Name Caption position bits (CPS0 to CPS4) Caption data latch completion flag 2 (CPS1)
Functions
After reset 0
RW RW
0: Data is not latched yet and a Indeterminate R -- clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (P33). 0 RW
6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7)
Caption Position Register
Address 00E616
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E916]
B
Name Count value (HC0 to HC4)
Functions
After reset 0
RW R--
0 to 4 5
Count source (HC5)
0: HSYNC signal 1: Composite sync signal f(XIN )/213 (1024 s, f(X IN) = 8 MHz)
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Sync Pulse Counter Register
Address 00E916
108
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Serial I/O mode register (SM) [Address 00EB16] B Name b1 0 0 1 1 Functions b0 0: f(XIN)/4 or f(XCIN)/4 1: f(XIN)/16 or f(XCIN)/16 0: f(XIN)/32 or f(XCIN)/32 1: f(XIN)/64 or f(XCIN)/64 After reset R W 0 RW
0, 1 Internal synchronous clock selection bits (SM0, SM1)
2 3
Synchronous clock selection bit (SM2) Port function selection bit (SM3)
0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT
0
RW
0
RW
4, 7 Fix these bits to "0." 5 6 Transfer direction selection bit (SM5) 0: LSB first 1: MSB first
0 0 0
RW RW RW
0: Input signal from S IN pin Transfer clock input pin selection bit (SM6) 1: Input signal from S OUT pin
Serial I/O Mode Register
Address 00EB16
A-D Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 1 (AD1) [Address 00EC16 ]
B
0 to 2
Name
Analog input pin selection bits (ADC10 to ADC12) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0: Do not set. 1:
After reset R W
0
RW
3, Nothing is assigned. This bits are write disable bits. 5 to 7 When these bits are read out, the values are "0." 0: Input voltage < reference voltage 4 Storage bit of comparison result (ADM4) 1: Input voltage > reference voltage
0 Indeterminate
R-- RW
AD Control Register 1
Address 00EC16
109
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED16]
B 0 to 5
Name D-A converter set bits (ADC20 to ADC25)
Functions
Reference voltage b5 b4 b3 b2 b1 b0 Vref
After reset 0
RW RW
0 0 0 1 1 1
0 0 0 1 1 1
0 0 0 1 1 1
0 0 0 1 1 1
0 0 1 0 1 1
0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0."
AD Control Register 2
Address 00ED16
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B Name 0 Timer 1 count source selection bit 1 (TM10) 1 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) Functions After reset R W 0: f(XIN)/16 or f(XCIN)/16 (Note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow 0 RW
2 3 4
0 0 0
RW RW RW
5
0
RW
6 7
0 0
RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 1
Address 00F416
110
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C716) b0 0 0 : f(XIN)/16 or f(XCIN)/16 (See note) 0 1 : f(XCIN) 1 0: External clock from TIM3 pin 1 1: b4 0 0 1 1 b1 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XIN)/2 or f(XCIN)/2 (See note) 1 : f(XCIN) After reset R W 0 RW
1, 4 Timer 4 count source selection bits (TM21, TM24)
0
RW
2 3 5 6 7
Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 6 of TM1
0 0 0 0 0
RW RW RW RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 2
Address 00F516
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616]
2
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
2
After reset
RW
Indeterminate R W
Note: To write data into the I C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
Address 00F616
111
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
I2C Address register
Address 00F716
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave receive mode 1 : Slave transmit mode 0 : Master receive mode 1 : Master transmit mode
After reset R W
Indeterminate 0 0 0 0 0 0
R-- R-- R-- R-- R-- RW RW
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannot be written.
I2C Status Register
Address 00F816
112
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00F916]
B
0 to 2
Name
Bit counter (Number of transmit/receive bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0: 1: 0: 1: 0: 1: 0: 1:
Functions
8 7 6 5 4 3 2 1
After reset R W
0
RW
3 4 5
I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD)
0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports
Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output.
I2C Control register
Address 00F916
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2) [Address 00FA16]
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4-CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F
...
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock
RW RW RW
6 7
0 0
Note: At 4000kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
I2C Clock Control Register
Address 00FA16
113
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00 CPU mode register (CPUM (CM)) [Address FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW
2
Stack page selection bit (CM2) (See note)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (X IN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN-XOUT selected (high-speed mode) 1: XCIN-XCOUT selected (high-speed mode)
1 0
0
RW
Note: This bit is set to "1" after the reset release.
CPU Mode Register
Address 00FB16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC 16] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV R--
0 : No interrupt request issued Timer 1 interrupt 1 : Interrupt request issued request bit (TM1R) Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 3 interrupt 1 : Interrupt request issued request bit (TM3R) 0 : No interrupt request issued Timer 4 interrupt 1 : Interrupt request issued request bit (TM4R) OSD interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit (OSDR) 0 : No interrupt request issued VSYNC interrupt request bit (VSCR) 1 : Interrupt request issued INT3 interrupt request 0 : No interrupt request issued bit (VSCR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
V: "0" can be set by software, but "1" cannot be set.
Interrupt Request Register 1
Address 00FC16
114
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV RW
INT1 interrupt request bit (INIR) 1 Data slicer interrupt request bit (DSR) 2 Serial I/O interrupt request bit (S1R) 3 f(XIN)/4096 interrupt request bit (CKR) 4 INT2 interrupt request bit (IN2R) 5 Multi-master I 2C-BUS interrupt request bit (IICR) 6 7 Timer 5 * 6 interrupt request bit (TM56R) Fix this bit to "0."
V: "0" can be set by software, but "1" cannot be set.
Interrupt Request Register 2
Address 00FD16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 1 2 3 4 5 6 7 Name Timer 1 interrupt enable bit (TM1E) Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt enable bit (TM3E) Timer 4 interrupt enable bit (TM4E) OSD interrupt enable bit (OSDE) VSYNC interrupt enable bit (VSCE) INT3 interrupt enable bit (IN3E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Interrupt Control Register 1
Address 00FE16
115
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 5 6 7 Name INT1 interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (SIE) f(XIN)/4096 interrupt enable bit (CKE) INT2 interrupt enable bit (IN2E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Multi-master I 2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled Timer 5 * 6 interrupt enable bit (TM56E) Timer 5 * 6 interrupt switch bit (TM56C) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6
Interrupt Control Register 2
Address 00FF16
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PM1) [Address 020816] B 0 Name PWM counts source selection bit (PM10) Functions 0 : Count source supply 1 : Count source stop After reset 0 RW RW
1, 2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- 4 to 7 When these bits are read out, the values are "0." 3 PWM output polarity selection bit (PM13) 0 : Positive polarity 1 : Negative polarity 0 RW
PWM Mode Register 1
Address 020816
116
MITSUBISHI MICROCOMPUTERS
M37273MF-XXXSP M37273EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 00 PWM mode register 2 (PM2) [Address 020916] B Name 0 P00/PWM0 output selection bit (PM20) 1 2 3 4 5 P01/PWM1 output selection bit (PM21) P02/PWM2 output selection bit (PM22) P03/PWM3 output selection bit (PM23) P04/PWM4 output selection bit (PM24) P05/PWM5 output selection bit (PW25) Functions 0 : P00 output 1 : PWM0 output 0 : P01 output 1 : PWM1 output 0 : P02 output 1 : PWM2 output 0 : P03 output 1 : PWM3 output 0 : P04 output 1 : PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 RW RW RW RW RW RW
6, 7 Fix these bits to "0."
PWM Mode Register 2
Address 020916
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E16] B
0 1 2 to 7
Name
Block 1 enable bit (RC0) Block 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0 0
RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
ROM Correction Enable Register
Address 020E16
117
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
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(c) 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1997. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
M37273MF-XXXSP, M37273EFSP DATA SHEET
Revision Description Rev. date 971130
(1/1)

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